Resets and Interrupts
Resets
MC68HC11E Family
—
Rev. 4
Technical Data
MOTOROLA
Resets and Interrupts
111
Complete this 2-step reset sequence to service the COP timer:
1.
Write $55 to COPRST to arm the COP timer clearing mechanism.
2.
Write $AA to COPRST to clear the COP timer.
Performing instructions between these two steps is possible as long
as both steps are completed in the correct sequence before the timer
times out.
5.3.4 Clock Monitor Reset
The clock monitor circuit is based on an internal resistor capacitor (RC)
time delay. If no MCU clock edges are detected within this RC time
delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled or disabled by the CME control bit in
the OPTION register. The presence of a timeout is determined by the RC
delay, which allows the clock monitor to operate without any MCU
clocks.
Clock monitor is used as a backup for the COP system. Because the
COP needs a clock to function, it is disabled when the clock stops.
Therefore, the clock monitor system can detect clock failures not
detected by the COP system.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E-clock frequency below 10 kHz
is detected as a clock monitor error. An E-clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E-clock is below 200 kHz is not recommended.
Address:
$103A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0