
Technical Data
MC68HC11E Family
—
Rev. 4
116
Resets and Interrupts
MOTOROLA
Resets and Interrupts
5.4.4 Real-Time Interrupt (RTI)
The real-time interrupt flag (RTIF) is cleared and automatic hardware
interrupts are masked. The rate control bits are cleared after reset and
can be initialized by software before the real-time interrupt (RTI) system
is used.
5.4.5 Pulse Accumulator
The pulse accumulator system is disabled at reset so that the pulse
accumulator input (PAI) pin defaults to being a general-purpose
input pin.
5.4.6 Computer Operating Properly (COP)
The COP watchdog system is enabled if the NOCOP control bit in the
CONFIG register is cleared and disabled if NOCOP is set. The COP rate
is set for the shortest duration timeout.
5.4.7 Serial Communications Interface (SCI)
The reset condition of the SCI system is independent of the operating
mode. At reset, the SCI baud rate control register (BAUD) is initialized to
$04. All transmit and receive interrupts are masked and both the
transmitter and receiver are disabled so the port pins default to being
general-purpose I/O lines. The SCI frame format is initialized to an 8-bit
character size. The send break and receiver wakeup functions are
disabled. The TDRE and TC status bits in the SCI status register (SCSR)
are both 1s, indicating that there is no transmit data in either the transmit
data register or the transmit serial shift register. The RDRF, IDLE, OR,
NF, FE, PF, and RAF receive-related status bits in the SCI control
register 2 (SCCR2) are cleared.