Technical Data
MC68HC11E Family
—
Rev. 4
60
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
INCB
Increment
Accumulator
B
Increment
Stack Pointer
Increment
Index Register
X
Increment
Index Register
Y
Jump
B + 1
B
B
INH
5C
—
2
—
—
—
—
—
INS
SP + 1
SP
INH
31
—
3
—
—
—
—
—
—
—
—
INX
IX + 1
IX
INH
08
—
3
—
—
—
—
—
—
—
INY
IY + 1
IY
INH
18
08
—
4
—
—
—
—
—
—
—
JMP (opr)
See Figure 3
–
2
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
7E
6E
6E
9D
BD
AD
AD
86
96
B6
A6
A6
C6
D6
F6
E6
E6
CC
DC
FC
EC
EC
8E
9E
BE
AE
AE
CE
DE
FE
EE
EE
CE
DE
FE
EE
EE
78
68
68
48
18
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
—
—
—
—
—
—
—
—
JSR (opr)
Jump to
Subroutine
See Figure 3
–
2
18
—
—
—
—
—
—
—
—
LDAA (opr)
Load
Accumulator
A
M
A
A
A
A
A
A
B
B
B
B
B
18
—
—
—
—
0
—
LDAB (opr)
Load
Accumulator
B
M
B
18
—
—
—
—
0
—
LDD (opr)
Load Double
Accumulator
D
M
A,M + 1
B
18
—
—
—
—
0
—
LDS (opr)
Load Stack
Pointer
M : M + 1
SP
18
—
—
—
—
0
—
LDX (opr)
Load Index
Register
X
M : M + 1
IX
CD
18
18
18
1A
18
—
—
—
—
0
—
LDY (opr)
Load Index
Register
Y
M : M + 1
IY
—
—
—
—
0
—
LSL (opr)
Logical Shift
Left
18
—
—
—
—
LSLA
Logical Shift
Left A
A
—
—
—
—
—
LSLB
Logical Shift
Left B
B
INH
58
—
2
—
—
—
—
LSLD
Logical Shift
Left Double
INH
05
—
3
—
—
—
—
LSR (opr)
Logical Shift
Right
EXT
IND,X
IND,Y
INH
74
64
64
44
18
hh ll
ff
ff
6
6
7
2
—
—
—
—
0
LSRA
Logical Shift
Right A
A
—
—
—
—
—
0
Table 3-2. Instruction Set (Sheet 4 of 7)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
C
0
b7
b0
A
B
b7
b0
C
0
b7
b0
C
0
b7
b0