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| 型號(hào)： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無(wú)SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門(mén)司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲(chǔ)器，無(wú)靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 9/38頁(yè) |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
9
Figure
5 - Drive port pins
from OMCs
A better solution would
be to use MCU I/O
mode, which bypasses the
OMC associated with a
port pin. This scenario
saves the OMC for other
uses as a buried node. In
this scheme, pin data is
written directly from the
MCU databus to the I/O
port, and pin data is read
directly from the I/O port
to the MCU data bus; see
Figure 6. Notice that the
OMCs in this arrangement are not linked to the I/O port or pin.
Figure 6 -
Drive port pin from
MCU I/O mode
Up to this point, we have
discussed how to access
port pins directly with the
MCU at run time
utilizing MCU I/O mode,
Address Out mode, and
Peripheral I/O mode.
Other entities within the
PSD can drive the port
pins in addition to the
MCU, and can be done
on a mixed basis. For
example, two of eight
port pins may be
controlled under MCU I/O mode while the remaining six are controlled by other means as defined in a
PSDabel file, e.g. an internal counter or shift register constructed from OMCs.
2.2.3 Implementing I/O Port Functions
A typical port pin has up to five internal drive sources.
←
MCU I/O via a
csiop
write by the MCU at run time
←
Address Out mode (Ports A and B only)
←
GPLD-OMC (Ports A, B, or C)
←
Peripheral I/O Mode (Port A only)
←
ECSPLD (Ports A, B, D)
Pins
I/O
Ports
AND
Array
MCU
Data Bus
PLD
Bus
MCU data write
Consumed
OMCs
Pins
I/O
Ports
FREE
OMCs
AND
Array
MCU
Data Bus
PLD
Bus
MCU data write
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