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參數(shù)資料
| 型號： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲器，無靜態(tài)存儲器） |
| 文件頁數(shù)： | 11/38頁 |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
11
Do this at run time:
At power on and reset, the MCU must initialize the port by writing 0x07 to the Port A
CONTROL
register, write 0x80 to the Port A
DIRECTION
register, and 0x88 to the Port A
DRIVE
register. Any time
after this initialization, the MCU can set or clear pin PA7 by writing to bit 8 of the Port A
DATA OUT
register
.
To read the state of pin PA5, the MCU can read the Port A
DATA IN
register and examine bit 5.
To use PA6 as a bi-directional pin, the MCU must first write the appropriate level to bit 6 of the Port A
DIRECTION
register (0 = input, 1 = output). PA6 may then be set, cleared, or read as described earlier
(see Table 1).
IMPORTANT:
The OMCs that underlie PA7, PA6, and PA5 are still available as buried nodes.
2.2.3.2 GPLD Out - Combinatorial
If the GPLD is used in a combinatorial mode, the state of the pin is dictated by NVM equations written in
the PSDabel file. An OMC is consumed in this mode.
Do this in the PSDabel file:
Declare the signal name 'Intr' as shown in line 55 of the sample design. Write equations. In the sample
design, a state machine defines the behavior of 'Intr' as shown in lines 235, 239, 244, and 249. When this
design is run through the PSDsoft fitter process, an OMC will be dedicated to 'Intr'.
Do this at run time:
Generally, the MCU will not affect the state of a combinatorial output pin at run time. Bit 4 of the Port A
CONTROL
and
DATAOUT
registers will have no effect. However, bit 4 of the Port A
DIRECTION
register
can
affect this pin because the direction signal from the MCU is logically ORed with the *.oe equation in
the PSDabel file. Therefore a "1" from one source may override a "0" from the other source (see OR gate on
OE control in Figure 3). Bit 4 of the Port A
DRIVE
register
will
affect this pin by changing its drive
characteristics (open-drain vs. standard CMOS).
2.2.3.3 Address Out Mode
In this mode, demultiplexed addresses are passed to external devices.
Do this in the PSDabel file:
Use the PSD Property statement to concisely define your intent. As shown in line 123 of the sample
design, use the Property statement this way:
WSIPSD Property Address_Out Aout[2:0]:Addr_out[2:0] PortA';
This statement assigns the signal names Addr_out[2:0] to Port A pins PA2, PA1, and PA0 respectively. It
also reserves these pins under these names so the fitter cannot use them for something else. No explicit pin
number assignment is necessary. No equations in the PSDabel file should be written for these signal
names.
Do this at run time:
At power on and reset, write 0x07 to the Port A
CONTROL
register to select Address Out mode for these
lines. Also, write 0x8F to the Port A
DIRECTION
register as shown in Table 1.
2.2.3.4 External Chip Select Mode (ECS Mode)
Fast decoding (faster than GPLD) of MCU address lines for external devices.
Do this in the PSDabel file:
Look in the PSD data sheets to see which pins support External Chip Select mode. Declare the signal for
an appropriate pin as shown on line 56 of the sample design. Write a decoding equation, as in line 207,
that contains only those parameters allowed for External Chip Select mode (see the PSD data sheets).
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