參數(shù)資料
型號(hào)： (Z)PSD813F3R
英文描述： Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無(wú)SRAM)
中文描述： 多芯片模塊的單片閃存部門(mén)司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲(chǔ)器，無(wú)靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 7/38頁(yè)
文件大?。?/td> 509K
代理商： (Z)PSD813F3R
PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
7
Figure 3 - PSD I/O Port
NOTE 1: (OUT MUX)
IF THIS PSD PORT PIN IS ON PORT A OR B, AND IF NO EQUATIONS FOR THIS PORT PIN EXIST IN THE PSDabel FILE, THEN THE MCU
CAN SET THE CONTROL BIT AT RUN TIME:
CONTROL = 1, LATCHED ADDR OUT SELECTED (MUX INPUT 2)
CONTROL = 0, MCU DATA OUT SELECTED, MCU I/O MODE (MUX INPUT 1)
IF THIS PSD PORT PIN IS ON PORT C OR D, AND IF NO EQUATIONS FOR THIS PORT PIN EXIST IN THE PSDabel FILE, THEN MCU DATA
OUT IS SELECTED (MUX INPUT 1). NO CONTROL BIT IS NEEDED OR AVAILABLE.
IF THIS PSD PORT PIN IS ON PORT A, AND EQUATIONS EXIST IN THE PSDabel FILE FOR PSEL1 OR PSEL0, AND BIT 7 OF THE VM
REGISITER IS SET (AT RUN TIME) TO ENABLE PERIPHERAL I/O MODE, THEN THE MCU DATA BIT IS SELECTED (MUX INPUT 3). THE
CONTROL BIT FROM THE MCU HAS NO EFFECT.
IF THIS PORT PIN IS ON PORT A, B, or C, AND IF EQUATIONS FOR THIS PORT PIN EXIST IN THE PSDabel FILE, THEN OUTPUT FROM
OMC (GPLD) IS SELECTED (MUX INPUT 4). THE CONTROL BIT FROM THE MCU HAS NO EFFECT.
IF THIS PSD PORT PIN IS ENABLED AS AN EXTERNAL CHIP SELECT (BY CHIP SELECT EQUATIONS IN THE PSDabel FILE), THEN ECS IS
SELECTED (MUX INPUT 5). ONLY AVAILABLE ON SOME PINS OF PORTS A, B, and D. THE CONTROL BIT FROM THE MCU HAS NO EFFECT.
NOTE 2: (OE MUX)
IF THIS PORT PIN IS ON PORT A, AND EQUATIONS EXIST IN THE PSDabel FILE FOR PSEL1 OR PSEL0 TO ALLOW PERIPHERAL I/O
MODE, THEN THE DIRECTION OF THIS PORT PIN IS CONTROLLED DYNAMICALLY BY MCU RD AND WR SIGNALS. OTHER DIRECTION
CONTROL FROM MCU OR PT HAS NO EFFECT. ONLY PORT A HAS THIS MULTIPLEXER AND PERIPHERAL I/O MODE.
NOTE 3: (PORT DATA BUFFER - PDB MUX)
IF THIS PSD PORT PIN IS ON PORT A,B,C,or D, AN MCU READ OF A PARTICULAR REGISTER IN THE CSIOP ARRAY WILL SELECT THE
APPROPRIATE SIGNAL TO PASS (MUX INPUTS 1 thru 6).
IF THIS PORT PIN IS ON PORT A, AND EQUATIONS EXIST IN THE PSDabel FILE FOR PSEL1 OR PSEL0, AND BIT 7 OF THE VM REGISITER
IS SET (AT RUN TIME) TO ENABLE PERIPHERAL I/O MODE, THEN THIS MUX WILL PASS PIN DATA TO THE MCU DATA BUS (VIA MUX
INPUT 6). MCU READS OF THE CSIOP ARRAY HAVE NO EFFECT (MUX INPUTS 1 thru 5 ARE NOT AVAILABLE).
I/O PORT (IOP)
O
U
T
M
U
X
P
D
B
M
U
X
DIRECTION
DRIVE
CONTROL
DATA OUT
ENABLE OUT
PIN DATA IN
D BIT, PERIPH I/O MODE, PORT A
PT OUTPUT ENABLE (.OE)
LATCHED ADDR BIT, PORTA & B
OE
MUX
OE
PSD PORT PIN
(TYPICAL PORTS
A,B,C)
EXTERNAL CHIP
SELECT, ESC
(AVAIL SOME PINS
OF PORTS A,B,D)
PSDsoft
CHIP LEVEL RESET
SEE
NOTE 3
SEE
NOTE 1
SEE
NOTE 2
INTERNAD BIT
4
OE CONTROL FROM THE MCU CAN BE
OVERRIDDEN BY THE PT OE CONTROL AND
VISA-VERSA
1
2
3
4
5
1
2
3
5
6
FROM OMC OUTPUT
TO IMC
FROM PLD INPUT
BUS
FROM AND ARRAY
FROM OMC
D
PORT A
& B ONLY
Q
D
Q
D
Q
D
Q
CLR
CLR
CLR
CLR
DIRECTION
DRIVE
CONTROL
DATA OUT
D BIT
WR\
D BIT
WR\
D BIT
WR\
D BIT
WR\
RESET
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