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參數(shù)資料
| 型號(hào)： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲(chǔ)器，無靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
8
The manipulation of the ports can occur at a granularity of less than one byte. For example, one nibble of
Port A can be input while the other nibble is output. In fact, a single port line (bit) can be input while the
rest are outputs, or vice versa. The ability to dynamically alter the direction on I/O port pins allows the
same pin to be utilized as input or output.
Peripheral I/O mode
is implemented with a combination of volatile and NVM configuration information.
In Peripheral I/O mode, all of Port A serves as a tri-state transceiver for the MCU data bus (much like a
74x245), see Figure 4. Once configured, Port A will track D0-D7 and allow other MCUs or peripherals to
share the local data bus without requiring external buffers and decoders. The direction is controlled
dynamically at run time by RD and WR signals derived from the MCU. The effective address range is
defined by equations written for the labels PSEL0 and PSEL1 in the PSDabel design file (NVM
information). This feature is enabled at run time (volatile information) by the MCU writing the appropriate
bit (bit 7) in the VM register of the
csiop
array. This feature is only available on Port A, see data sheets for
more detail.
Figure 4 - Peripheral I/O Mode
2.2.2 I/O Port Tips
An important concept to keep in mind is that a PSD port pin may be used for one function (MCU I/O,
Address Out, latched IMC input, etc.) while the underlying OMC may be used for internal logic as a
buried node.
The following examples show use of 4 bits in a block. However, the PSD assets can be grouped as small
as 1 bit or as large as 8 bits.
If the designer's intent is to drive port pins from the MCU, it could be implemented as shown in Figure 5.
The OMC outputs are tied to the pins through I/O ports. This method consumes the OMC as well as the
I/O port.
MCU RD
MCU WR
VM REG, BIT 7
PSEL0
PSEL1
MCU DATA BUS,
D7 - D0
PA7 - PA0
8
8
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| ZPSD813F3V-15J | 制造商:WSI 功能描述: |
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