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參數(shù)資料
| 型號： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲器，無靜態(tài)存儲器） |
| 文件頁數(shù)： | 5/38頁 |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
5
1.1 Purpose
The purpose of this application note is varied.
1. Provide a framework for application of a PSD.
2. Describe some of the original thinking behind the creation of the GPLD logic block.
3. Present a strategy to efficiently apply the PSD resources to solve user design problems.
4. Explain the differences between input MicroCells (IMC) and output MicroCells (OMC).
5. Provide examples of the use of IMCs and OMCs.
6. Highlight PSDsoft commands (development tool)
7. Provide unity between the design concept (what I want to do) and the design
implementation (how to get the PSD to do it).
1.2 Philosophy
There are many assets available to the designer in the GPLD. However, the most versatile of these assets
is the OMC. This document takes the approach that, since the OMC is the most versatile, it should be
conserved as far into the design process as possible. This approach results in the highest functional
efficiency of the PSD, maximizing the òbang for the buckó.
So, as a general rule, dont consume the OMCs first, save them for last.
1.3 Design strategy
The GPLD is consists of four main components: the AND array, I/O Ports, IMCs and OMCs. Each
component has its own attributes to optimize the realization of the users design. The choice and
application of these components are controlled by declarations and equations, which are composed and
compiled in PSDsoft
(a development tool).
PSDsoft offers design entry in a hardware description language (HDL) format based on ABEL, an industry
standard. The designer will enter the design using PSDabel, compile it, and map it to the silicon on the
PSD. This mapping is called the fitting process.
The best fit is the one that gains maximum utility from the PSD, taking advantage of the layered assets
within the PSD. As you will see in the design example of Appendix A, many of the PSD pins are using
IMCs while the underlying OMCs are used for other logic (state machine, loadable counter, etc.)
2.0 GPLD Assets
The functional blocks of the GPLD, as shown in Figure 2, are grouped to make up the entire GPLD as
shown in Figure 1. This section describes the individual blocks that comprise the GPLD.
2.1 AND Array
The GPLD AND array (as seen in Figures 1 and 2) is used to form product terms (PTs) specified by using
the PSDabel tool in the PSDsoft development system. This AND array has 63 inputs for the
PSD6XX/7XX and 73 inputs for the PSD8XX. The inputs come from the PLD input bus as shown in the
figures. Each input signal has both true and compliment levels available. Typical inputs are MCU address
and control, PSD page register bits, feedback from nodes, and pins, etc (See individual data sheets for
signal descriptions.)
The PSD8XX features a FLASH based AND array, while the other families are EPROM based.
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