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參數(shù)資料
| 型號： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲器，無靜態(tài)存儲器） |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
23
9.
After PSD Configuration is complete, exit this section. Under PSDsoft choose PSD
Compile. Under Compile choose Fit (map design to silicon). If the fit was successful, then choose
Address Translate to create a file (*.obj) to program into the PSD device on a device programmer.
The Address Translate utility blends your MCU compiler/linker output with the PSD
configuration.
10.
11.
Simulate if desired.
Program the part.
12.
Iterate steps 9 through 13 until it works. As the design firms up, lock down pin
assignments by specifying pin numbers in the PSDabel design file. While using the fitting utility
iteratively, you can always disregard the pin number assignments by the use of the òIgnoreó
command of the Compile Tool (See "Troubleshooting", secion 2.5.4)
2.5.3 Fitter Issues
When creating a design, it is useful to realize that the fitter does not always see all the information that
goes into the PSDabel file at design entry.
The first compile stage from within 'PSDabel Design Entry' passes a processed version of the original
design to the fitter stage. Consequently, the only view the fitter has of the designers intent is through the
compiled PSDabel output file. If PSDabel optimizes away some critical parameter or signal, the fitter
cannot take action on it because the fitter simply does not have the visibility of the designers intent.
One method to ensure fitter visibility at design entry is to use WSIPSD PROPERTY. This special
command is not acted upon by the PSDabel engine and is passed transparently (from PSDabels
perspective) to the fitter.
Another visibility issue with the fitter is that the fitter can only create logic using inputs that are
configurable and available at design time (NVM bits). Any bits that can be manipulated at run time are not
available for fitter use since they may change under MCU control.
From a perspective internal to the chip, the fitter can only utilize internal NVM bits that direct the
interconnection of silicon in the PSD. The fitter cannot see or use any volatile bit associated with the
csiop
array.
2.5.4 Troubleshooting
What if my design compiles (in Design Entry Tool), but produces a lot of errors
The Design Entry Compile is essentially a label correlation and syntactical check done by PSDabel. That
is,
←
Are all the labels defined
←
Has PSDabel syntax been used consistently throughout the file
←
Are definitions in the correct file section
Start with the first error and correct it. Sometimes errors cascade (flow from the first error) and subsequent
errors may magically disappear after the initial error is corrected.
What if my design does not fit ('Fit' in the Compile Tool)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD813F3V-15J | 制造商:WSI 功能描述: |
| ZPSD813F3V-A-15J | 制造商:WSI 功能描述: |
| ZPSD813F4-12JI | 制造商:WSI 功能描述: |
| ZPSD813F4-15J | 制造商:WSI 功能描述: 制造商:STMicroelectronics 功能描述:microcontroller peripheral devices 制造商:STMicroelectronics 功能描述:Flash in-system programmable microcontroller peripheral device |
| ZPSD813F4-90J | 制造商:WSI 功能描述: |
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