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參數(shù)資料
| 型號： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲器，無靜態(tài)存儲器） |
| 文件頁數(shù)： | 3/38頁 |
| 文件大小： | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
3
1.0 OVERVIEW
A PSD (Programmable System Device) is a peripheral device, which provides memory, logic, I/O, and
other functions to a microcontroller unit (MCU). Internally, the PSD is a collection of programmable logic
surrounding both volatile and non-volatile memory (NVM). Some of this logic is dedicated to specific
MCU functions, such as bus interfacing, address demultiplexing, and address decoding. These functions are
encompassed by the Decode PLD (DPLD) and External Chip Select PLD (ECSPLD) as shown in Figure 1.
Much of the remaining logic is not dedicated to MCU interfacing, making it available to solve user design
problems. The block used for general logic is called the General PLD (GPLD), also shown in Figure 1.
The GPLD is comprised of Input MicroCells (IMCs), Output MicroCells (OMCs), and an AND array. The
GPLD is tied to the I/O Ports as well. Many of the elements in the GPLD are directly accessible by the
MCU. The central focus of this document is based on the GPLD portion of the PSD.
This document is applicable to the PSD6XX, PSD7XX, and PSD8XX PSD families. The general
architecture of the GPLD in these devices is very similar. The PSD8XX devices are FLASH based and offer
4 more OMCs than the PSD6XX/7XX. For this document, we will illustrate the use of a PSD6XX.
Appendix A consists of a sample design based on a PSD611. This design highlights many features and is
referenced by line number and signal name throughout this primer.
Figure 1 Top Level Block Diagram, PSD6XX
The block diagram shown in Figure 2 depicts a portion of the GPLD. In a general sense, each PSD port
pin is linked to the functional blocks as shown. The blocks include an IMC, an OMC, the AND array, and
the associated I/O Port. For example, one could visualize Figure 2 as 1/8 of PSD Port A. Notice that the
MCU bus is directly linked to most of the elements.
PD0
PD1
PD2
I/O PORT
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O PORT
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O PORT
PC0
PC1
PC3
PC4
PC5
PC6
PC7
I/O PORT
SRAM
4Kbit - Batt B/U
AD0
AD1
AD2
AD3
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
MCU
ADDR/
DATA
MCU
CONTROL
CNTL0
CNTL1
CNTL2
(PD0)
POWER MANGMNT
APD / CMISER
(GPLD)
23 INPUT
MICRO<>CELLS
12 OUTPUT
MICRO<>CELLS
PAGE REG
EXTERNAL CS
PLD (ECSPLD)
RUNTIME CONTROL
CSIOP REG FILE
SECURITY
LOCK
PLD INGEPLD
ALLO-
CATOR
EPROM
8 BLOCKS
256K-1Mbit total
PIN FEEDBACK
EXTERNAL CHIP SELECTS (7)
PERIPHERAL I/O MODE SELECTS
RS0
ES0-7
CSIOP
NODE FEEDBACK
WSi PSD6XX
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO MCU
DECODE
PLD (DPLD)
AND
ARRAY
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