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參數(shù)資料
| 型號(hào)： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲(chǔ)器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲(chǔ)器，無靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
13
Figure 7 - Input MicroCell (IMC)
The IMC allows a port pin signal to participate as an input to the AND array for general use. The IMC
also makes the state of the pin directly accessible to to MCU data bus. A unique aspect of the IMC is that
it will pass the signal to the AND array and MCU by one of three ways:
←
Clocked through an edge-triggered register (edge-latched input)
←
Gated through a transparent latch (level-latched input)
←
Passed straight through (pass-through input)
Edge-latched inputs are good for synchronizing an input signal to given clock edge. You will see in the
sample design that this feature is used to debounce noisy keypad inputs so they can become stable inputs
to an internal state machine.
Level-latched inputs are good for passing additional high order address signals to the AND array for address
decoding. These high order address signals may be gated with the ALE/AS signal from the MCU.
Pass-through inputs allow an external signal to participate as an input to the AND array directly. Pass-
through inputs also provide a feedback path for a signal generated by MCU I/O output mode.
Notice in Figure 7 that the method of passing a signal through an IMC (edge, level, pass) is determined by
NVM bits set by PSDsoft. This is true for the clock source as well. These settings cannot be altered at run
time. However, the state of a signal that has passed through an IMC may be read asynchronously by the
MCU at run time. Each PSD port has an
IMC
register in the
csiop
array. For example, all eight Port A
IMCs may be read at
csiop
+0x0A, Port B at
csiop
+0x0B, and Port C at
csiop
+0x18.
Note: Port D pins do not have IMCs. However, Port D signals may be used as AND
array inputs directly (no latching) from an external source. Additionally, Port D pins
operate in MCU I/O mode and they can be fed back to the AND array.
INPUT MICROCELL (IMC)
D
Q
G
D
Q
M
U
X
M
U
X
PSDsoft
DATA BIT TO MCU
MCU READ OF PARTICULAR CSIOP IMC REGISTER
PT LATCH/GATE (.LD OR .LE)
PIN INPUT
LATCHED INPUT
(.LD)
(.LE)
ALE OR AS
PSDsoft
ALE OR AS
INTERNAL ADDR, DATA, CNTL BUS LINKED TO MCU
PSD PORT PIN
TO I/O PORT
BLOCK
FROM AND ARRAY
TO AND ARRAY
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