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參數(shù)資料
| 型號： | (Z)PSD813F3R |
| 英文描述： | Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM) |
| 中文描述： | 多芯片模塊的單片閃存部門司（閃速，在系統(tǒng)可編程微控制器外圍器件，分位閃速存儲器，無靜態(tài)存儲器） |
| 文件頁數(shù)： | 6/38頁 |
| 文件大小： | 509K |
| 代理商： | (Z)PSD813F3R |
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PSD GPLD Primer - PSD6XX/7XX/8XX é Application Note
055
WSi Inc. Fremont CA 800-832-6974 www.wsipsd.com
6
2.2 I/O Ports
The intent of the I/O Port is to provide a convenient method to control inputs and outputs on the port pins
of a PSD, see Figure 3. PSD ports A, B, and C have similar I/O port structures. Port D has a subset of this
structure (see data sheets for differences). A port pin can be controlled at run time by the MCU via a byte-
wide volatile relocatable array whose base is named
csiop
. A port pin can also be controlled directly by
functions within the PSD silicon which are programmed with NVM bits by PSDsoft, independent of the
MCU. These NVM bits determine such functionality as multiplexed/non-multiplexed MCU data,
8bit/16bit MCU data, pin output source (logic), pin input destination (AND array), etc. In some cases, the
MCU may override NVM PSD configuration or operations at run time by writing to the
csiop
registers
(such as control of pin output enables, loading OMCs, mapping memory, etc.)
2.2.1 I/O Port Operating Modes
As shown in Figure 3, I/O pin control occurs via registers within the I/O port that the MCU can write to at
run time. The MCU accesses these registers by writing or reading the
csiop
array. Some bytes in the
csiop
array are devoted to the
control
of the port pins (e.g. direction, control, drive, etc.) That is, how the port
functions. Other bytes are devoted to the actual information on the pin itself, which we call
data
.
Registers in the
csiop
array are written or read based on the desired operation. For example, to change the
state of a pin on Port A, the MCU would write a byte with the appropriate bit pattern to the
DATA OUT
register at csiop+0x04. To read a pin of Port A, the MCU would read a byte from the
DATA IN
register at
csiop+0x00, and examine the appropriate bit. Whether the port is an input or an output is controlled via
the
DIRECTION
register at csiop+0x06 (0 = input, 1 = output). These functions comprise the
MCU I/O
mode
.
Note: The address offsets given as examples above are based on an 8-bit MCU design.
The offsets will differ for 16-bit Motorola MCU designs. See the PSD data sheets for
the definition of all registers within the
csiop
array.
For pins on ports A and B only, the
CONTROL
register bits determine the run time function of the port
pins. When
CONTROL
bits are one, the corresponding pins will output demultiplexed address signals to
external devices. This mode is referred to as
Address Out mode
. When the
CONTROL
bits are zero, the
pins will operate in MCU I/O mode. PSD ports C and D do not have
CONTROL
bits, as a result, MCU
I/O mode is the only run time mode available.
Note: For either MCU I/O mode or Address Out mode, the PSDabel design file should
contain no equations for the pins. The design file should only declare the pin names so
the fitter utility does not use the pins for something else. This allows the MCU to
control the pins at run time.
The pin drive type is controlled by writes to the
DRIVE
register in the
csiop
array. The MCU may define
the pin characteristics as open drain, or fast slew rate. Not all port pins support this feature, see data sheets
for pin applicability and specifications.
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