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參數(shù)資料
| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 72/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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CHAPTER 8 TEST FUNCTIONS
72
8.2 Normal Mode
This is the mode normally used by the user.
When the low level is input to the BUNRI pin, pins other than test pins become valid and the normal mode is
entered. At this time, inputs to the TBI22 to TBI0 pins are ignored, and the TBO42 to TBO0 pins go into high
impedance.
8.3 Unit Test Mode and Standby Test Mode
When the high level is input to the BUNRI pin, inputs to pins other than test pins are ignored (become invalid), and
the system enters the test mode. There are two test modes, the unit test mode and the standby test mode.
Perform circuit design so that the bus configuration pins (except test pins) do not become floating level or cause
bus contention during the unit test mode and the standby test mode. (For details on the status of pins in each mode,
see
Section 2.2 Pin Statuses
.)
8.3.1 Unit test mode
When the high level is input to the BUNRI pin and the TEST pin, the system enters the unit test mode. In the unit
test mode, inputs to pins other than test pins are ignored, and inputs to the TBI22 to TBI0 pins become valid instead.
Moreover, values for the pins other than test pins are output to the TBO42 to TBO0 pins.
Caution
The unit test mode is a mode for testing performed by NEC.
8.3.2 Standby test mode
When the high level is input to the BUNRI pin and the low level is input to the TEST pin, the system enters the
standby test mode.
This mode is used for cores that are not tested during test circuit verification simulation and user logic separation
simulation.
Inputs to the TBI22 to TBI0 pins are ignored and the TBO42 to TBO0 pins go into high impedance.
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