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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 49/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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CHAPTER 4 BUS CONTROL FUNCTIONS
49
4.2 Interface between V30MZ and I/O
The segment system is not applied to an I/O address like memory.
In I/O address output timing, 0 is output to all the higher 4 bits (A19 to A16) of the address bus.
Data can be transferred between the V30MZ and I/O in either byte units or word units and both an 8-bit I/O device
and 16-bit I/O device can be connected. However, like memory for a word data access, 1 bus cycle for an even
address and 2 bus cycles for an odd address are used.
When accessing an 8-bit I/O device, A0 of the I/O address information is only used for device selection and values
higher than A1 are used for device selection and selection of several registers within one device. That is, all the
internal registers of the I/O device at an even address are also even and all the internal registers of the I/O device at
an odd address are selected with an odd number.
Use of a memory mapped I/O configuration (using the memory area by allocating it for I/O) allows the I/O to be
placed in a 1 M-byte memory space not in the I/O space.
Using the memory mapped I/O configuration, it is possible to perform a variety of addressing modes and operation
processing for the memory directly to the I/O device.
Caution
However, with the memory mapped I/O, all control signals output from the V30MZ are for the
memory and so the I/O device is distinguished only by address information. Therefore, special
care is required to avoid contention between the addresses of variables and static data, etc.,
and the addresses allocated to the I/O.
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