參數(shù)資料
型號(hào)： V30MZ
英文描述： V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002]
中文描述： V30MZ（TM）硬件（初步）|用戶(hù)手冊(cè)[01/2002]
文件頁(yè)數(shù)： 52/89頁(yè)
文件大小： 418K
代理商： V30MZ
CHAPTER 4 BUS CONTROL FUNCTIONS
52
4.3.2 Write timing of memory and I/O
The V30MZ outputs the address (A19 to A0), UBEB signal, bus status (BS3 to BS0), and data (DO15 to DO0) in
synchronization with the rising edge of the clock (CLK).
Then at the next rising edge of the CLK signal, it samples the READYB signal. If the READYB signal is low at this
time, the operation goes to the next bus cycle, and if the READYB signal is high, the operation goes to the wait cycle
(TW), and the current bus cycle is extended. In the TW state, invalid data is output from the DO15 to DO0 pins.
Therefore, if a TW state is inserted to extend the bus cycle, latch the data from the DO15 to DO0 pins output at the
first bus cycle using an external circuit.
Moreover, in the TW state, the A19 to A0 signals and the UBEB signal maintain their output value, but the BS3 to
BS0 signals become high level.
Figure 4-3. Write Timing of Memory and I/O (1/2)
(a) With No Wait
CLK (input)
BS3 (output)
DO15 to DO0 (output)
READYB (input)
T
X
Don't care
Don't care
BS2 (output)
BS1 (output)
BS0 (output)
H
During memory write: H
During I/O write: L
During memory write: L
During I/O write: H
A19 to A0 (output)
UBEB (output)
Remark
{
indicates the sampling timing.
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