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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 20/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 2 PIN FUNCTIONS
20
This pin does not go into high-impedance.
The BS3 pin has the same functions as the IO/M pin of the V30HL, except for output timing (only names differ).
Table 2-2. Relationship between BS3 to BS0 Signal and Bus Cycle
Pin Output Level
BS3
BS2
BS1
BS0
Bus Cycle (Status)
L
L
L
L
Interrupt acknowledge
L
H
L
H
I/O read
L
H
H
L
I/O write
H
L
L
L
Standby (HALT) mode
H
L
L
H
Memory data read
H
L
H
L
Memory data write
H
H
L
H
Code fetch
H
H
H
H
Idle status
Remarks 1.
L: Low level
H: High level
2.
No output with combinations other than above.
(6) READYB (Ready)...Input
Performs wait control.
When memory or I/O data read/write operation cannot be completed within the basic bus cycle (1 clock), the bus
cycle can be extended by inputting an inactive level (high level) to this pin.
(7) BUSLOCKB (Bus lock)...Output
It outputs a low-active signal to other bus masters requesting that they do not use the system bus during
execution of 1 instruction following the BUSLOCK instruction. It also outputs the signal during interrupt
acknowledge.
It does not go into high impedance.
(8) POLLB (Poll)...Input
It is used to synchronize between program execution by the V30MZ and operation of an external device. Input to
this pin are checked by the POLL instruction: if a low level is input, the next instruction is processed; if a high
level is input, program execution is halted until this pin is driven low.
Input of a low level to this pin should be done for at least 9 clocks.
(9) RESET (Reset)...Input
Inputs a reset signal. Following reset release, the V30MZ starts program execution from memory address
FFFF0H (segment value: FFFFH, offset value: 0000H).
(10)HLDRQ (Hold request)...Input
Inputs a signal to the V30MZ to request that the external bus master release the address bus, data bus, and
control bus (bus hold).
Inputting a high level to this pin causes the bus hold acknowledge status to be entered upon completion of the
currently executing bus cycle, and while the high level is input, the bus hold acknowledge status continues.
Input a high level for at least 3 clock cycles.
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