- 您現在的位置：買賣IC網 > PDF目錄361638 > V30MZ V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] PDF資料下載
參數資料
| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數： | 48/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁當前第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
CHAPTER 4 BUS CONTROL FUNCTIONS
48
(2) When accessing word data at even address
Word data is accessed in 1-bus cycle with UBEB = 0 and A0 = 0.
Table 4-1 shows the relationship between the type of operand and the number of UBEB, A0 pins, and bus cycles.
Table 4-1. V30MZ Data Access
Operand
UBEB pin output level
A0 pin output level
Number of Bus Cycles
Word at even address
L
L
1
Word at odd address
1st bus cycle
L
H
2
2nd bus cycle
H
L
Byte at even address
H
L
1
Byte at odd address
L
H
1
Remark
L : low level
H : high level
Normally, the V30MZ performs an access (prefetch) of an operation code in word units. However, when a branch
to an odd address takes place, only 1 byte at that odd address is fetched and subsequent bytes are fetched again in
word units again.
When a vector table address is generated from the vector number (0 to 225), an even address is always
generated, and so an access to the interrupt vector table is always performed as word data at an even address.
Therefore, a vector table access to one interrupt is always performed in 2 bus cycles for the 2 words of the segment
base and offset.
4.1.1 Cautions on accessing word data
When accessing word data by the V30MZ, ensure that all the data that can be checked by the program may be
placed at an even address. When it is placed at an odd address, the result will be as follows.
One bus cycle for a memory access requires 1 clock. Therefore, every time word data at an odd address is
accessed, one extra clock of the instruction execution time are required compared to accessing word data at an even
address. This applies when executing an instruction that has more than one word data access.
In the case of a word data transfer from memory to memory, 2 memory accesses are required for a read from the
source and a write to the destination and so the execution time becomes the maximum when both are odd
addresses.
This problem of odd addresses also happens in stack manipulation. Registers, etc. are automatically saved to the
stack by interrupt servicing, but these are all word data and so when processed at an odd address, note that the
number of bus cycles is doubled and the interrupt response time is delayed.
Example:
Number of execution clocks of MOV reg, mem instruction
Byte data : 1
Word data : 2 (For odd address)
: 1 (For even address)
This is an example in which one word data access is performed.
相關PDF資料 |
PDF描述 |
|---|---|
| V32FB-V42D-MMMME | MODEM Chip Set |
| DSP16A-F14-033 | 16-Bit Digital Signal Processor |
| DSP16A-F14-033I | 16-Bit Digital Signal Processor |
| DSP16A-F14-055 | 16-Bit Digital Signal Processor |
| DSP16A-F14-055I | 16-Bit Digital Signal Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| V30N | 制造商:Renesas Electronics Corporation 功能描述: |
| V-30TB | 制造商:Mencom 功能描述: |
| V31 | 制造商:SMC Corporation of America 功能描述:CONNECTOR |
| V3-1 | 功能描述:基本/快動開關 15.1A pin plunger Screw Terminals RoHS:否 制造商:Omron Electronics 觸點形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級:IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| V3-1001 | 功能描述:基本/快動開關 Snap Action SPDT 10A 3.89N Thru-Hole RoHS:否 制造商:Omron Electronics 觸點形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級:IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
發(fā)布緊急采購，3分鐘左右您將得到回復。