參數(shù)資料
型號: V30MZ
英文描述: V30MZ(TM) Hardware (Preliminary) | User's Manual[01/2002]
中文描述: V30MZ(TM)硬件(初步)|用戶手冊[01/2002]
文件頁數(shù): 54/89頁
文件大?。?/td> 418K
代理商: V30MZ
CHAPTER 4 BUS CONTROL FUNCTIONS
54
4.4 Bus Hold Function
When a high level is input to the HLDRQ pin, the HLDAK signal becomes high level at the end of the bus cycle
that is currently being executed, and the V30MZ enters the bus hold state (TH). However, an idle cycle (TI) lasting 1
clock is always inserted immediately before the TH state.
In the TH state, the A19 to A0 signals, the UBEB signal, and the BS3 to BS0 signal become high level, but the
DO15 to DO0 signals output undefined data.
Next, when a low level is input to the HLDRQ pin, the HLDAK signal becomes low level, and the V30MZ returns to
the normal bus cycle. However, a TI state lasting 1 clock is always inserted immediately after the TH state.
In the TH state, no code fetch cycle is generated.
Figure 4-4. Bus Hold Timing
CLK (input)
A19 to A0 (output)
UBEB (output)
BS3 to BS0 (output)
DO15 to DO0 (output)
READYB (input)
Tx
TI
TW
Valid
Don't
care
Don't
care
TH
TH
TH
HLDRQ (input)
HLDAK (output)
T
X
Don't care
TI
TH
Invalid
Remark
{
indicates the sampling timing.
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