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參數(shù)資料
| 型號(hào)： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊(cè)[01/2002] |
| 文件頁數(shù)： | 59/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 5 INTERRUPT FUNCTIONS
59
Figure 5-2. Interrupt Acknowledge Cycle
CLK (input)
A19 to A0 (output)
BS0 (output)
DI15 to DI0 (input)
1st bus
cycle
TI
TI
Invalid
Invalid
Invalid
TI
TI
BUSLOCKB (output)
2nd bus
cycle
Invalid
Interrupt
vector
number
BS3 (output)
BS2 (output)
BS1 (output)
UBEB (output)
H
(1)
The 1st bus cycle is activated to obtain synchronization with the external interrupt controller. The values
read from the data bus (DI15 to DI0) are not used.
At this time, address 00000H is output to the address bus (A19 to A0), but this value has no meaning.
Moreover, a wait cycle can be inserted by using the READYB signal.
Four clocks of idle cycle (TI) are inserted between the 1st bus cycle and the 2nd bus cycle. During this
interval, the BUSLOCKB signal remains low. No code fetch cycle is generated between the 1st bus cycle
and the 2nd bus cycle.
The V30MZ reads the vector number from the interrupt controller during the 2nd bus cycle (only lower byte
of data bus is valid). At this time, address 00000H is output to the address bus, but this value is
meaningless.
Moreover, similarly to the 1st bus cycle, a wait cycle can be inserted by using the READYB signal.
(2)
(3)
Remark
Whereas in the case of the V30HL, UBE output is always low level during the interrupt acknowledge
cycle, in the case of the V30MZ, UBEB output is always high level. (UBEB output becomes low level
only when the start address of the interrupt processing routine is read.)
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