參數(shù)資料
型號： V30MZ
英文描述： V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002]
中文描述： V30MZ（TM）硬件（初步）|用戶手冊[01/2002]
文件頁數(shù)： 15/89頁
文件大小： 418K
代理商： V30MZ
CHAPTER 1 GENERAL DESCRIPTION
15
(2/3)
Item
V30MZ
V30HL
V30MX
Supported instructions
The V30MZ does not support the following instructions supported by the V30HL and
V30MX. An undefined result is obtained by executing these instructions.
ADD4S, BRKEM, CALLN, CLR1
REPNC, RETEM, ROL4, ROR4, SET1
Moreover, the FPO1 instruction is handled as an NOP instruction.
Up to 7 instruction prefixes can be used (for all
instructions). Even if instruction prefixes are used
redundantly, normal processing is performed as long
as their total number doesn't exceed 7.
If there are more than 7 prefixes for one instruction,
the execution result of the instruction (to which
prefixes have been attached) is not guaranteed.
Furthermore, normal recovery from interrupt
processing is not possible.
Note 1
, CMP4S, EXT, FPO2, INS, NOT1
Note 2
, REPC,
Note 3
, SUB4S, TEST1
Number of instruction prefixes
For repeat string instructions
(REP, MOVBK, etc.), 3 types of
prefixes MAX. can be used (REP
is also counted as 1 type). If there
are redundant instruction prefixes,
repeat string instructions cannot
be performed normally after the
end of interrupt processing. In the
case of instructions other than
string instructions, the number of
instruction prefixes is not limited.
Decimal correction operation is
performed regardless of the value
of the second byte of the CVTDB
and CVTBD instructions.
All 8 bits of the number of shifts
(immediate, or specification by CL
register) are valid.
All 8 bits of the second operand
are valid.
Except for SP, 7 memory read
cycles are performed.
Memory read is performed in the
order IY
→
IX.
Decimal correction instruction
Performs a correction operation for the second byte of
CVTDB and DVTBD instructions.
Multiple bit shift and
rotate instructions
Only the lower 5 bits of the number of shifts are valid.
PREPARE instruction
Only the lower 5 bits of the second operand are valid.
POP R instruction
Executes memory read cycle 8 times. However, data
corresponding to SP is not used.
Memory read is performed in the order IX
→
IY
Repeat prefixed CMPBK,
CMPBKB, and CMPBKW
instructions
CALL memptr32 instruction
Reads new PC, PS values after saving current PC,
PS values to the stack.
Current PC and PS values are
saved on to the stack after the
new PC and PS values are read.
If the operand is memory, only the
read cycle is performed, and the
write cycle of the shift result is not
performed. For the SHL, SHR, and
SARA instructions, the Z flag, P
flag, and S flag do not change.
These flags retain the status prior
to instruction execution.
When number of shifts = 0 for
shift, and rotate instructions
Executes also write cycle of memory operand. Z flag,
P flag, and S flag change for SHL, SHR, and SARA
instructions. These flags are set/cleared depending
on the execution result of shift instruction.
Notes 1.
Excluding CLR1 CY and CLR1 DIR.
2.
Excluding NOT1 CY.
3.
Excluding SET1 CY and SET1 DIR.
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