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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 55/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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55
CHAPTER 5 INTERRUPT FUNCTIONS
Interrupts of the V30MZ are roughly divided into two kinds; hardware interrupts and software interrupts. These
interrupts are all vectored interrupts that reference a vector table. An interrupt vector table stores the start address of
an interrupt service routine.
When an interrupt is generated, the V30MZ references the fixed 4 bytes (fixed vector) in the vector table
corresponding to the interrupt source or any 4 bytes (variable vector) specified each time and branches to the
address stored there (start address of the interrupt service routine).
The interrupt vector table is assigned to a 1 K-byte area 000H to 3FFH of the memory space and can define a
maximum of 256 vectors.
Table 5-1 shows the number of interrupt source clocks processed, vector numbers and priority order.
Figure 5-1 shows the interrupt vector table configuration.
Table 5-1. Interrupt Source List
Interrupt Source
Number of Clocks
Processed
Note
Vector No.
Priority Order
NMI input (rising edge active)
26
2
2
Hardware
interrupt
INT input (high level active)
32
32 to 255
3
DIV or DIVU instruction divide error
0
CHKIND instruction boundary over
5
BRKV instruction
4
BRK 3 instruction
3
BRK imm8 instruction
32 to 255
1
Software
interrupt
BRK flag (single-step)
25
1
4
Note
The number of clocks after execution of an instruction is aborted by an interrupt until the program branches
to the start address of the interrupt service routine (progression of the wait state into the memory bus cycle
and bus hold request are not taken into account).
Remark
The following three instructions have a relatively long execution time, and even if an interrupt request is
generated during their execution, their execution is not interrupted, and the interrupt request is
acknowledged after the execution is completed. This point should be paid attention to in the case of
systems for which the interrupt response time is particularly crucial.
Instruction
Number of Execution
Clocks
Remarks
DIVU
24
When divide error not generated due to DIVU instruction
When divide error not generated due to DIV instruction
When 2nd operand = 31
DIV
25
PREPARE
139
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