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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 62/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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CHAPTER 5 INTERRUPT FUNCTIONS
62
5.4 Interrupt Servicing in Execution of Block Processing Instruction
When a hardware interrupt request is generated in execution of a primitive block transfer/comparison, or input
instruction, the V30MZ acknowledges it and branches to the corresponding interrupt address.
However, in a block processing instruction, immediately after completion of the bus cycle in which an interrupt is
generated, the interrupt may not be acknowledged. In that case, it takes several bus cycles after generation of the
interrupt until the V30MZ can acknowledge the interrupt. Table 5-2 shows the number of bus cycles. In this table,
the bus cycle in which an interrupt is generated is counted as the first bus cycle.
Table 5-2. Number of Bus Cycles Required until Interrupt is Acknowledged
Instruction
IX Register
IY Register
Number of Bus Cycles Required until Interrupt is Acknowledged
MOVBKW
Even
Even
2 to 4
Even
Odd
3 to 6
Odd
Even
2 to 5
Odd
Odd
3 to 7
MOVBKB
–
–
2 to 4
CMPBKW
Even
Even
1, 2
Even
Odd
1 to 3
Odd
Even
1 to 3
Odd
Odd
1 to 4
CMPBKB
–
–
1, 2
CMPMW
–
Even
1
–
Odd
1, 2
CMPMB
–
–
1
LDMW
Even
–
1
Odd
–
1, 2
LDMB
–
–
1
STMW
–
Even
3, 4
–
Odd
3 to 5
STMB
–
–
3, 4
Example 1.
When an interrupt request is generated in execution of MOVBKB instruction
MOVBKB bus cycle
Interrupt servicing
INT input or NMI input
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