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參數(shù)資料
| 型號(hào)： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊(cè)[01/2002] |
| 文件頁數(shù)： | 14/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 1 GENERAL DESCRIPTION
14
1.3 Differences between V30MZ and V30HL, V30MX
(1/3)
Item
V30MZ
V30HL
V30MX
Address/data bus
A19 to A0, DI15 to DI0, DO15 to DO0
A19 to A16,
AD15 to AD0
Provided
A23 to A0, D15
to D0
Not provided
Large-scale mode/small-scale
mode
Pin functions
Not provided
Following pins of V30HL are removed
ASTB, PS3 to PS0, BUFEN, QS1, QS0, BUFR/W, RD, IC, RQ/AK1,
RQ/AK0, INTAK, S/LG, LBS0, WR, NC
Not provided
Not possible
Note
:
—
μ
PD8080AF emulation function
Connection to numerical
operation co-processor
LIM EMS4.0 function
Test function as CBIC core
Provided
Possible
Not provided
Not provided
Provided (TBI22 to TBI0, TBO42 to TBO0, BUNRI,
TEST)
High-level output
Not provided
Not provided
Provided
Provided
BUSLOCKB pin status in case
of BUSLOCK instruction
execution prior to HALT
instruction
Status of UBEB pin during
interrupt acknowledge cycle
Status of output pins during bus
hold
Relationship between
BUSLOCK instruction and bus
hold request
Low-level output
High-level output
Low-level output
See section
2.2. Pin Statuses
High impedance
Bus hold request is acknowledged even if BUSLOCK
instruction is executed immediately before an
instruction that does not perform access to memory
or I/O. The BUSLOCKB output remains high.
Not possible
BUSLOCK instruction effective for
all instructions
Bus hold request acknowledged
between first and second bus
cycle when odd address word
data is accessed
Bus status output at recovery
from bus hold status to standby
mode
Instruction execution time
Possible
No (remains in idle status)
Provided
The number of instruction clocks for each instruction and the CPU operating frequency of
the V30MZ have been improved, so that the instruction execution time is considerably
reduced. Note that programs that depend on the number of instruction execution clocks,
such as consecutive I/O accesses, may not function normally.
The V30MZ performs pipeline processing internally, executing multiple instruction in
parallel. Therefore, in cases such as when a hardware interrupt synchronized with a given
bus cycle is requested, the V30MZ may acknowledge the interrupt request after performing
a larger number of instructions than the V30HL and V30MX. However, this does not apply
with regard to I/O accesses
If an arithmetic operation defined as an indefinite flag change is executed, the contents of
the flag immediately after the execution may differ from the V30HL and V30MX. This is
especially likely to occur in the case of multiply and divide instruction.
The timing at which interrupt requests are not acknowledged differs. (Refer to
Section 5.3
Timing at which Interrupt is Not Acknowledged
.)
Interrupt response time
Undefined flag change
Interrupt request acknowledge
disable timing
Note
The BS3 pin of the V30MZ has the same functions as the IO/M pin of the V30HL, except for the output timing.
Remark
Active low pins are indicated with xxx (overscore added) in the case of the V30HL, whereas they are
indicated with xxxB (B added) in the case of the V30MZ.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V30N | 制造商:Renesas Electronics Corporation 功能描述: |
| V-30TB | 制造商:Mencom 功能描述: |
| V31 | 制造商:SMC Corporation of America 功能描述:CONNECTOR |
| V3-1 | 功能描述:基本/快動(dòng)開關(guān) 15.1A pin plunger Screw Terminals RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
| V3-1001 | 功能描述:基本/快動(dòng)開關(guān) Snap Action SPDT 10A 3.89N Thru-Hole RoHS:否 制造商:Omron Electronics 觸點(diǎn)形式:SPDT 執(zhí)行器:Lever 電流額定值:5 A 電壓額定值 AC:250 V 電壓額定值 DC:30 V 功率額定值: 工作力:120 g IP 等級(jí):IP 67 NEMA 額定值: 端接類型:Wire 安裝:Panel |
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