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參數(shù)資料
| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 21/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 2 PIN FUNCTIONS
21
(11)HLDAK (Hold acknowledge)...Output
Outputs a signal indicating that the HLDRQ signal has been acknowledged and that the bus hold acknowledge
status is entered.
(12)NMI (Non-maskable interrupt)...Input
Inputs a non-maskable interrupt signal by software.
The NMI signal is active at the rising edge and detected in any clock cycle, however, it starts interrupt servicing
after the end of the instruction being executed.
The interrupt start address for this interrupt is determined by interrupt vector 2.
Input an active level (high level) for at least 5 cycles after a rising edge.
When inputting NMI requests consecutively, keep NMI low for at least one clock cycle.
The priority order of interrupt request signals is as follows.
INT < NMI < HLDRQ
Remark
The standby mode can also be released by an NMI signal.
(13)INT (Interrupt request)...Input
Inputs an interrupt request signal that can be masked by software.
Input an active level (high level) to this until the interrupt acknowledge status is output from the BS3-BS0 pins.
(14)CLK (Clock)...Input
Inputs a clock signal. Input to this CLK pin and internal operation of the V30MZ are performed at the same
frequency.
When the CLK input is stopped, the supply current enters 0A.
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