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| 型號(hào)： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊(cè)[01/2002] |
| 文件頁數(shù)： | 19/89頁 |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 2 PIN FUNCTIONS
19
2.3 Description of Pin Statuses
2.3.1 Normal pins
(1) A19 to A0 (Address)...Output
Bus for outputting 20-bit address.
None of the pins ever go into high impedance.
(2) DI15 to DI0 (Data input)...Input
Dedicated input bus for inputting 16-bit data.
Always input high-level or low-level signal (do not make signal high impedance).
(3) DO15 to DO0 (Data output)...Output
Dedicated output bus for outputting 16-bit data.
None of the pins ever go into high impedance.
(4) UBEB (Upper byte enable)...Output
Outputs low-active signal indicating that higher 8 bits of 16-bit data bus are to be used with memory or I/O
access cycle. This pin does not go into high impedance.
The bus cycles for which this signal becomes active are as follows.
Bus cycle through byte access of odd address
Bus cycle through first byte access of odd address for word data
Bus cycle through access of even address for word data
Combined with the A0 signal, the bus cycle can be identified as follows.
Table 2-1. Relationship among Operand and UBEB, A0, and Bus Cycles
Operand
UBEB pin output level
A0 pin output level
Number of bus cycles
Even address word
L
L
1
1st bus cycle
L
H
2
Odd address word
2nd bus cycle
H
L
Even address byte
H
L
1
Odd address byte
L
H
1
Remark
L: Low level
H: High level
(5) BS3 to BS0 (Bus status)...Output
Outputs status signal to external to notify state of the bus cycle. During reset and bus hold acknowledge, go into
idle state (high-level output).
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