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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 61/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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CHAPTER 5 INTERRUPT FUNCTIONS
61
5.3 Timing at which Interrupt is Not Acknowledged
In the timing shown in (1) to (4) below, that is, between an instruction in which data is directly set in the segment
register or 3 types of prefix and the following one instruction, no hardware interrupt or BRK flag (single-step) interrupt
is acknowledged. Furthermore, only the INT interrupt is not acknowledged in the timing shown in (5).
With the following 5 timings, no interrupt is acknowledged.
(1)
(2)
(3)
(4)
(5)
Between each of MOV SS, reg 16; MOV SS, mem16; POP SS instructions and the next instruction
Between segment override prefix (PS:, SS:, DS0:, DS1:) and the next instruction
Between repeat prefix (REP, REPE, REPNE) and the next instruction
Between BUSLOCK instruction and the next instruction
Between each of EI, RETI, and POP PSW instructions (in case an IE flag of the PSW register is set (1) by
executing the instruction) and the next instruction (only INT interrupt)
However, an NMI request signal generated in interrupt disable timings in (1) to (4) is held pending internally and
acknowledged after execution of the next one instruction is completed.
Moreover, if the timing of (5) is generated with an IE flag set, the INT interrupt is acknowledged even immediately
after the execution of these instructions.
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