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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 96/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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327
3.4.35 DTF First and Continue Register at A4h
This register defaults to 0000 0000h and is set to 0000 0000h on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
031
DTF_First&Continue
W/O
Write DTF first and continue. This write-only register provides the host with the capability to write the
quadlets of a transmit packet, except the last quadlet, to the DTF.
3.4.36 DTF Update Register at A8h
This register defaults to 0000 0000h and is set to 0000 0000h on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
031
DTF_Update
W/O
DTF update. This write-only register provides the host with the capability to write the last quadlet of a
transmit packet to DTF. Once written, the packet is transmitted.
3.4.37 DRF Data Read Register at ACh
This register defaults to 0000 0000h and is set to 0000 0000h on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
031
DRFRead
R/O
DRF data read access register. This read-only register provides the host with the capability to read the
data quadlet of a received packet from the DRF. Each read outputs the next quadlet from the DRF. If the
DRF is empty, the last valid value is read.
3.4.38 DTF Control Registers at B0h, B4h, B8h, and BCh
The values in this register are N/A when DTpktz = 0 at 90h. Unless otherwise specified, these registers default to
0000 0000h and, except for the specified bits, are unaffected by a bus reset.
3.4.38.1 DTF Control Register 0 at B0h
BITS
ACRONYM
DIR
DESCRIPTION
0
DTFCTL0
R/W
DTF packetizer transmit control. This bit depends on the current bus condition. Table 3-2 describes the
read and write values of this control bit.
1
DTFCTL1
R/W
DTF packetizer transmit control. This bit depends on the current bus condition. Table 3-2 describes the
read and write values of this control bit.
2
DTFClr/DTFst
R/W
DTF clear control bit (write)/DTFStatus transmit (read).
DTF clear control bit: When DTFClr is set to 1, data in the DTF is cleared. This bit is set to 0 automatically
after the DTF is cleared. DTFClr/DTFst must not be asserted when DTFCtl is busy. When this bit is read it
specifies the current transfer transaction status. DTF packetizer transfer status: DTFSt represents the
DTF transaction status data. When set to 1 this bit indicates that the transaction is active.
Note: DTF_destination_ID (B8h) data is required before this bit is set to 1.
3
DTFNdIdval
R/O
DTF NodeID valid. This bit represents a valid NodeID in DTF destination ID. Writing to DTF destination ID
(bits 015 at B8h) sets this bit to 1, and a bus reset clears this bit to 0. This bit should be 1 when the
DTF_destination_ID at B8h is reset. This bit defaults to 0 and is set to 0 on a bus reset.
4
DTFNotify
R/W
DTF notify. When this bit is set to 1, transaction status data is transferred after the DTF data transfer.
5
Reserved
N/C
Reserved
67
DTF Spd
R/W
DTF transaction speed. DTF Spd specifies the speed used by the DTF packetizer.
00 : 100 Mbps
01 : 200 Mbps
10 : 400 Mbps
11 : Not valid
811
DTF Max Payload
R/W
DTF transfer maximum payload. DTF Max Payload is used to calculate the maximum data transfer length
that the DTF packetizer requests in a single write transaction.
The maximum data transfer length (in bytes) is 2(DTF Max Payload + 2).
12
PgTblEn
R/W
Page table enable. PgTblEn controls page table fetching. When PgTblEn is set to 1, page table fetching is
enabled. DTF_destination_offset_hi and DTF_destination_offset_lo data point to the page table address.
When PgTblEn is 0 and AutoPg is set to 1, page table fetching is disabled. DTF_destination_offset_hi
(B8h) and DTF_destination_offset_lo (BCh) determine the data area.
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