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參數(shù)資料
| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 56/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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17
1.4.5
Power Supplies
TERMINAL
DESCRIPTION
NAME
PGE NO.
GGW NO.
DESCRIPTION
AGN[5:1]
109, 104, 98,
93, 90
A16, D17, G14,
H17, K16
Analog ground. These terminals must be tied together to the low-impedance circuit board
ground plane.
AVD[5:1]
110, 105, 101,
94, 89
B15, D16, F15,
H16, K15
Analog circuit power terminals. A combination of high-frequency decoupling capacitors
near each terminal is suggested, such as paralleled 0.1-
F and 0.001-F capacitors.
These supply terminals are separated from PWTST, VDD3V, and VDPLL internal to the
device to provide noise isolation.
PWTST
15, 31, 47, 63,
80, 87, 118,
126, 141
B9, C4, C11,
H3, L17, N16,
P1, U6, U12
1.8-V Vdd power terminals. A combination of high-frequency decoupling capacitors near
each terminal is suggested, such as paralleled 0.1-uF and 0.001-uF capacitors. These
supply terminals are separated from VDD3V, AVD, and VDPLL internal to the device to
provide noise isolation (this voltage is not supplied when the internal regulator is enabled.)
VDD3V
10, 24, 33, 38,
52, 66, 70, 79,
128, 144
A2, B8, F2, L3,
N15, P3, R8,
T3, U13, U15
3.3-V Vdd. A combination of high frequency decoupling capacitors near each terminal is
suggested, such as paralleled 0.1-uF and 0.001-
F capacitors. These supply terminals
are separated from PWTST, AVD, and VDPLL internal to the device to provide noise
isolation.
VDPLL
113
C13
PLL power supply. A combination of high-frequency decoupling capacitors near each
terminal is suggested, such as paralleled 0.1-
F and 0.001-F capacitors. These supply
terminals are separated from PWTST, VDD3V, and AVD internal to the device to provide
noise isolation.
VSPLL
114
B13
PLL ground. These terminals must be tied together to the low-impedance circuit board
ground plane.
VSS
3, 11, 19, 27,
35, 43, 51, 59,
67, 75, 83, 88,
117, 123, 131,
140
B4, B7, B10,
D3, D11, G3,
K1, K17, M3,
M16, R2, R5,
R10, R13, R17,
U8
Digital ground. These terminals must be tied together to the low-impedance circuit board
ground plane.
1.4.6
Miscellaneous
TERMINAL
NAME
PGE
NO.
GGW
NO.
I/O
DESCRIPTION
EN
32
P2
I/O/
Hi-Z
Internal 1.8-V regulator enable. This terminal enables the internal 1.8-V regulator. Tie low during
normal/operational mode.
MODE[2:0]
4, 2, 1
D2,
C1, B1
I
Chip mode select. MODE[2:0] = 000 is the normal/operational mode. All other modes are for test
purposes and are not described in this data sheet.
PHYTESTM
143
B3
I
Test mode. This input terminal is used in manufacturing tests. Tie high during normal/operational
mode.
PLLON
137
B5
I
PLL enable. This signal forces the internal phase-locked loop (PLL) on when it is asserted, even
during ultralowpower mode and power-down mode. If this signal is deasserted, the PLL operates
only during regular device operation.
XRESETL
85
L15
I
Link reset. Reset for link block
XRESETP
86
L16
I
PHY reset. Reset for PHY block
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參數(shù)描述 |
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| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AB21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER |
| TSB43AB21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
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