參數(shù)資料
型號： TSB43AA82PGE
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 100/146頁
文件大?。?/td> 770K
代理商： TSB43AA82PGE
331
3.4.40.2 99 DRF Control Register 1 at C4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_BlockCount/
DRF_BlockSize
R/W
DRF receive block size in bytes / DRF receive block count.
When LngBlk in DMA control (90h) is set to 1, this value is DRF_BlockSize.
When LngBlk is set to 0, this value is DRF_BlockCount. DRF_BlockSize specifies the received blocksize
value. DRF_BlockCount specifies the number of received blocks. DRF_BlockCount is decremented
during reception automatically.
3.4.40.3 DRF Control Register 2 at C8h
BITS
ACRONYM
DIR
DESCRIPTION
016
DRF_destination_ID
R/W
DRF transfer destination ID. DRF_destination_ID specifies the transferred destination ID.
1731
DRF_destination_offset_hi
R/W
DRF transfer destination start offset high. DRF_destination_offset_hi specifies the transferred
destination offset high.
3.4.40.4 DRF Control Register 3 at CCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_destination_offset_lo
R/W
DRF receive destination start offset low. DRF_destination_offset_lo specifies the transferred
destination offset low.
3.4.41 DRF Header Registers at D0h, D4h, D8h, and DCh
If DRHStr at 90h bit 27 is set to 1, the stripped header is written to these registers. These registers default to
0000 0000h and are unaffected by a bus reset.
3.4.41.1 DRF Header Register 0 at D0h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header0
R/O
DRF header 0. First quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the first header quadlet of a received packet header after the header has been copied into
DRF_Header0.
3.4.41.2 DRF Header Register 1 at D4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header1
R/O
DRF header 1. Second quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the second header quadlet of a received packet header after the header has been copied into
DRF_Header1.
3.4.41.3 DRF Header Register 2 at D8h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header2
R/O
DRF header 2. Third quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the third header quadlet of a received packet header after the header has been copied into
DRF_Header2.
3.4.41.4 DRF Header Register 3 at DCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_Header3
R/O
DRF header 3. Fourth quadlet of received packet header in DRF. When DRHStr at 90h is set to 1, the host
can read the fourth header quadlet of a received packet header after the header has been copied into
DRF_Header3.
相關(guān)PDF資料
PDF描述
TSB43AA82GGW 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176
TSB43DA42GHCR PCI BUS CONTROLLER, PBGA196
TSB500SK02 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
TSB500SK10MDS 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
TSB5000331DS 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB43AA82PGEG4 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AB21 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER
TSB43AB21A 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
TSB43AB21A-EP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic Integrated 1394a-2000 OCHI pHY/Link-Layer Controller
TSB43AB21AI 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*