參數(shù)資料
型號： TSB43AA82PGE
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 49/146頁
文件大?。?/td> 770K
代理商： TSB43AA82PGE
142
14.2 Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
Differential input voltage, VID
Cable inputs, during data reception
118
260
mV
Differential input voltage, VID
Cable inputs, during arbitration
168
265
mV
Common-mode input voltage, VIC
TPB cable inputs, source power node
0.4706
2.515
V
Common-mode input voltage, VIC
TPB cable inputs, nonsource power node
0.4706
2.015
V
Output current, IO
TPBIAS outputs
–5.6
1.3
mA
Power-up reset time, tpu
XRESETP input
2
ms
TPA, TPB cable inputs, S100 operation
±1.08
Receive input jitter
TPA, TPB cable inputs, S200 operation
±0.5
ns
Receive input jitter
TPA, TPB cable inputs, S400 operation
±0.315
ns
Between TPA and TPB cable inputs, S100 operation
±0.8
Receive input skew
Between TPA and TPB cable inputs, S200 operation
±0.55
ns
Receive input skew
Between TPA and TPB cable inputs, S400 operation
±0.5
ns
For a node that does not source power, see Section 4.2.2.2 in IEEE P1394a.
14.3 Electrical Characteristics Over Recommended Ranges of Operating Conditions
(Unless Otherwise Noted)
14.3.1 Device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLLON/PD/LPS/ENZ = L/L/L/L, PWTST = NC
2.1
mA
PLLON/PD/LPS/ENZ = H/L/L/L, PWTST = NC
11.2
mA
IDD-ULP
Supply current—ULP (ultralow power)
(see Note 1)
PLLON/PD/LPS/ENZ = L/L/L/H,
51
A
IDD-ULP
Supply current—ULP (ultralow power)
(see Note 1)
PLLON/PD/LPS/ENZ = L/L/L/H,
PWTST = 1.8 V
51
A
(see Note 1)
PLLON/PD/LPS/ENZ = H/L/L/H,
9.3
mA
PLLON/PD/LPS/ENZ = H/L/L/H,
PWTST = 1.8 V
9.3
mA
PLLON/PD/LPS/ENZ = L/H/X/L
2.1
mA
IDD-PD
Supply current—PD (power down)
PLLON/PD/LPS/ENZ = H/H/X/L
11.0
mA
IDD-PD
Supply current—PD (power down)
(see Note 2)
PLLON/PD/LPS/ENZ = L/H/X/H
51
Α
(see Note 2)
PLLON/PD/LPS/ENZ = H/H/X/H
9.3
mA
Supply current—(PLLON/PD/LPS/ENZ =
Ports disabled
30.4
IDD
Supply current—(PLLON/PD/LPS/ENZ =
X/L/H/L)
One port enabled
46.6
mA
IDD
X/L/H/L)
Two ports enabled
62.6
mA
IDD-op
Supply current—transmitting/receiving
One port enabled
48.0
mA
IDD-op
Supply current—transmitting/receiving
16 bit data through BDI (packets 512 bytes)
Two ports enabled
64.0
mA
VTH
Power status threshold, CPS input
400-k
resistor
4.7
7.5
V
II
Input current, LPS, PD, PHYTESTM,
PWRCLS
[0:2]
VDD = 3.6-V
5
A
IIRST
Pullup current, XRESETP input
VI = 1.5-V or 0-V
–90
–20
A
VO
TPBIAS output voltage
At rated IO current
1.665
2.015
V
NOTES:
1. Ultralow-power (LPS = L): Using LPS to enable a low-power mode allows the user not to provide a reset when disabling the
low-power mode. In this mode, the user must provide the 1.8-V core voltage, externally (ENZ = H, PWTST = 1.8 V) or internally
(ENZ = L, PWTST = NC, decoupling caps).
2. Power-down mode (PD = H): When power-down mode is disabled, a reset must be applied to the device.
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