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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 79/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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312
3.4.10 Time Limit Register at 28h
This register defaults to 0320 08E0h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
015
SplitTimeOut
R/W
Split transaction time-out. SplitTimeOut limits the time waiting for the response packet.
If the response packet is not received when the split transaction timer exceeds the SplitTimeOut period,
the transaction failed. Unit is one Iso cycle (125
s). This field defaults to 0320h and is unaffected by a bus
reset.
1623
RetryInterval
R/W
Retry interval time. RetryInterval defines the time from the receipt of ack_busy_X to retransmission. Unit is
one Iso cycle (125
s). This field defaults to 08h and is unaffected by a bus reset.
2427
RtryLmt
R/W
Retry limit. RtryLmt limits the number of times the transmitter retries. If RtryLmt is 0, the transmitter shall
not attempt retransmission of the busied packet. Otherwise, it retransmits the packet RtryLmt times or until
the receipt of acknowledgements other than ack_busy_X. This field defaults to Eh and is unaffected by a
bus reset.does
2831
ORBTimer
R/W
Time elapsed by timer to fetch command block ORB. The timer to fetch command block ORB waits for
ORBTimer period before transmitting the read request packet. Unit is one Iso cycle (125
s). This field
defaults to 0h and is unaffected by a bus reset.
3.4.11 ATF Status Register at 2Ch
This register defaults to 1000 0080h and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
ATFFul
R/O
ATF full flag. When the ATF is full, ATFFul is set to 1 and writes are ignored. Otherwise, ATFFul is set to 0.
This bit defaults to 0 and is set to 0 on a bus reset.
1
ATFAFl
R/O
ATF almost-full flag. While the ATF can accept at least one more quadlet write, ATFAFl is set to 1.
Otherwise ATFAFl is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
2
ATFAEm
R/O
ATF almost-empty flag. While the ATF contains only one quadlet, ATFAEm is set to 1. Otherwise, ATFAEm
is set to 0. This bit defaults to 0 and is set to 0 on a bus reset.
3
ATFEmp
R/O
ATF empty flag. When the ATF is empty, ATFEmp is set to 1. Otherwise ATFEmp is set to 0. This bit
defaults to 1 and is set to 1 on a bus reset.
418
Reserved
N/A
Reserved
19
ATFClr
S/C
ATF clear control bit. When ATFClr is set to 1, the ATF is cleared. This bit is cleared automatically once the
ATF is cleared. This bit defaults to 0 and is cleared on a bus reset.
2022
Reserved
N/A
Reserved
2331
ATF_Size
R/W
ATF size control bits. ATF_Size is equal to the ATF size number in quadlets. This field defaults to 80h and is
unaffected by a bus reset.
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