- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄199479 > TSB43AA82PGE (TEXAS INSTRUMENTS INC) 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 63/146頁 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁當(dāng)前第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁
23
2.7
Packet Distributor
The packet distributor module provides the packet routing service for each FIFO module. In SBP-2 mode, all request
and response packets are properly routed to the correct FIFO, and sent to corresponding initiators. In direct print
protocol (DPP) mode, the packet distributor filters a request packet by its address and then saves it into the correct
receive FIFO.
2.8
Packetizer
The packetizer module provides packetization for a transmit packet. The data stream from the DMA FIFO is split into
small packets that meet the SBP-2 requirements. A read or write request header is attached to each packet with a
correctly incremented destination address. The transaction/timer manager provides busy retry and split transaction
timer control if required. The packetizer also provides auto-page table fetch service. The internal auto-fetch module
sends a read request to the present page address, and the DMA automatically sends data to the requested address
set by the Page Table Element. At the end of packetizer, if the DMA function has successfully completed, the DMA
automatically sends a status block packet.
2.9
Configuration ROM
The ConfigROM provides the configuration ROM required by the IEEE 1212 standard2. The ConfigROM module
supports the auto response service for a ConfigROM read request and records the transaction history. The host
controller can load ConfigROM data during node initialization. Once initialized, the ConfigROM is accessible by peer
node read requests. See Section 5 for more details.
2.10 Link Core
The link core provides link layer service such as correctly formatted IEEE 1394-19953 and IEEE 1394a-20004
asynchronous transmit and receive packets. It also generates and inspects the 32-bit cyclic redundancy check
(CRC). This link core does not support isochronous service.
2.11 PHY (and PHY Interface)
The TSB43AA82 has an integrated 400-Mbps two-port physical layer. The PHYsical (PHY) interface provides
PHY-level service to the link layer service. See Section 11 for more details.
2.12 FIFOs
The TSB43AA82 has three FIFO types, asynchronous command FIFOs, configuration ROM FIFOs and DMA FIFOs.
These FIFO types have maximum sizes of 378 quadlets, 126 quadlets, and 1182 quadlets respectively. Except for
the MTQ and MRF, the FIFO sizes are adjustable. The sum of all the FIFOs in a type must not exceed the maximum
size. See Section 4 for more information on the asynchronous command FIFOs, Section 5 for more information on
ConfigROM/LOG FIFOs, and Section 8 for more information on BDFIFOs.
2 IEEE Std 1212-1991, IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses
3 IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus
4 IEEE Std 1394a-2000, IEEE Standard for a High Performance Serial Bus - Amendment 1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB43AA82GGW | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| TSB43DA42GHCR | PCI BUS CONTROLLER, PBGA196 |
| TSB500SK02 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB500SK10MDS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000331DS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AB21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER |
| TSB43AB21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
| TSB43AB21A-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic Integrated 1394a-2000 OCHI pHY/Link-Layer Controller |
| TSB43AB21AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。