- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄199479 > TSB43AA82PGE (TEXAS INSTRUMENTS INC) 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 90/146頁 |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁當(dāng)前第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁
322
3.4.25.3 Transaction Timer Status Register 3 at 6Ch
BITS
ACRONYM
DIR
DESCRIPTION
03
tCode
R/O
TimerNo’s transmitting tCode. The tCode of the packet that the timer defined by TimrNo at 60h is
transmitting or has transmitted in the last transaction.
45
Spd
R/O
TimerNo’s transmitting speed. The speed of the packet that timer defined by TimrNo at 60h is transmitting
or has transmitted in the last transaction.
611
tLabel
R/O
TimerNo’s transmitting tLabel. The tLabel of the packet that the timer defined by TimrNo at 60h is
transmitting or has transmitted in the last transaction.
1215
Retry_Counter
R/O
TimerNo’s transmitting retry counter. The limit set by the Retry_Counter of the packet that the timer defined
by TimrNo at 60h is transmitting or has transmitted in the last transaction.
1631
SplitTrTimer
R/O
TimerNo’s transmitting split transaction timer. The SplitTrTimer period that the timer defined by TimrNo at
60h is waiting or has waited for the response packet in the last transaction. This timer increments on the
cycle-start packets.
3.4.26 Write-First, Write-Continue, and Write-Update Registers at 70h, 74h, 78h
These registers default to 0000 0000h and are set to 0000 0000h on a bus reset.
3.4.26.1 Write-First Register at 70h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_First
W/O
Write the first quadlet of the packet to ATF, MTQ or CTQ. This write-only register provides the host with the
capability to write the first quadlet of a transmit packet to the transmitting FIFO.
The values of tLabel and tCode determine to which FIFO (ATF,MTQ or CTQ) the written packet is
delivered.
3.4.26.2 Write-Continue Register at 74h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_Continue
W/O
Write any quadlet other than the first or the last quadlet to ATF, MTQ or CTQ. This write-only register
provides the host with the capability to write any quadlet other than the first or last of a transmit packet to the
transmitting FIFO.The transmitting FIFO was determined when the host wrote to the Write_First (70h)
register.
3.4.26.3 Write-Update Register at 78h
BITS
ACRONYM
DIR
DESCRIPTION
031
Write_Update
W/O
Write the last quadlet of the packet. This-write only register provides the host with the capability to write the
last quadlet of a transmit packet to transmitting FIFO. The transmitting FIFO was determined when the
host wrote to the Write_First (70h) register.
3.4.27 Reserved at 7Ch
3.4.28 ARF, MRF, and CRF Data Read Registers at 80h, 84h, 88h
These registers default to 0000 0000h and are set to 0000 0000h on a bus reset.
3.4.28.1 ARF Data Read Register at 80h
BITS
ACRONYM
DIR
DESCRIPTION
031
ARFRead
R/O
ARF data read access register. This read-only register provides the host with the capability to read a
quadlet of the received packet from the ARF. Each read outputs the next quadlet from the ARF. If the ARF is
empty, the last valid value is read.
3.4.28.2 MRF Data Read Register at 84h
BITS
ACRONYM
DIR
DESCRIPTION
031
MRFRead
R/O
MRF data read access register. This read-only register provides the host with the capability to read a
quadlet of the received packet from the MRF. Each read outputs the next quadlet from the MRF. If the MRF
is empty, the last valid value is read.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB43AA82GGW | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA176 |
| TSB43DA42GHCR | PCI BUS CONTROLLER, PBGA196 |
| TSB500SK02 | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB500SK10MDS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
| TSB5000331DS | 30 A, BARRIER STRIP TERMINAL BLOCK, 1 ROW, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AB21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER |
| TSB43AB21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
| TSB43AB21A-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic Integrated 1394a-2000 OCHI pHY/Link-Layer Controller |
| TSB43AB21AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。