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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 143/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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84
Table 83. Status-Block Format Descriptions
FIELD NAME
DESCRIPTION
AsAgent
Associates corresponding agent for this transaction. The difference between associated and nonassociated is
whether the status transfer is successful or not successful. The agent status specified by agent number falls into a
dead state. Setting AsAgent to 0 activates the AsAgent and changes agentnum.
agentnum
Specifies the agent number associated by this transaction.
destination_offset_high,
destination_offset_low
The concatenation of these two fields addresses a quadlet in the destination node address space. This address must
be quadlet aligned (modulo 4) and the address of the status FIFO at the initiator.
data_length
data_length is the number of bytes of status block size transmitted in the packet.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the IEEE 1394-1995
standard.
status Block
SBP-2 status block. Refer to the SBP-2 standard for more information.
To load status block packet into internal RAM:
1.
Set the size of status block FIFO in the MTXBufSiz bit (94h). For example, to set 8 quadlets of the entire
status block packet, write 06h to this field. This field should be half the size of the status block packet in
quadlets.
2.
Set internal RAM to write status mode. DTFST/DRFST bits (F8h) enable access to the status FIFO. Once
one of the bits is set to 1, the host can access the status FIFO.
3.
Write the status block packet. The host can write the status block packet through the log data register (FCh).
Address requests written to FCh are processed automatically.
4.
Activate the status block. Set the notify bit enable to send the status block packet. Notify bits are located
at DTF and DRF control registers.
8.4
DMA Operation
8.4.1
Packet Transmission by DTF
There are three modes of packet transmission with DTF:
Writing to the CFR through the microcontroller
Through the bulky interface in direct mode (DTPktz at 90h = 0)
Through the bulky interface in packetizer mode (DTPktz at 90h = 1)
8.4.1.1 Packet Transmission by Writing to the CFR Through the Microcontroller
By clearing the DTDSel bit (90h, bit 29), the host can write a packet to DTF using DTF_First&Continue (A4h) and
DTF_update (A8h). In this case, the DMA bulky interface can not write data to the DTF.
Set DTFEn (90h, bit 3) to 1 and DTPktz (90h, bit 5) to 0 to enable DTF transmission through the
microcontroller.
Set DTHdIs (90h, bit 24) to 0 to disable header insertion.
Set DTDSel (90h, bit 29) to 0 to switch to CFR packet write mode.
Write a packet excluding the last quadlet into DTF first and continue register (A4h). This complies with the
DTF format defined in Section 8.2.2.
Start the transmission request by writing the last quadlet to the DTF update register (A8h).
At the completion of a packet transmission, DTAVal is set and an appropriate acknowledgement is displayed
on DTxAck (A0h).
When DTSpDis (90h, bit 7) is 1, or no split transaction has occurred, a DTFEnd interrupt is created to end
the transmission transaction.
When DTSpDis (90h, bit 7) is 0 and split transaction(s) has occurred, a DTFEnd interrupt is created to end
the transmission transaction after a response packet is received.
In this case, a response packet is received by DRF.
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