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參數(shù)資料
| 型號： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 93/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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324
BITS
DESCRIPTION
DIR
ACRONYM
14
CheckPg
R/W
Check page table. When CheckPg is set to 1, page table entry consistency with the configuration ROM is
checked. If any error is observed, an interrupt is initiated, and DTFEnd or DRFEnd set is to 1.
15
AutoPg
R/W
AutoPaging. When AutoPg is set to 1, the auto paging function is enabled. Page table read requests are
automatically initiated. This bit defaults to 1 and is unaffected by a bus reset.
1618
DRPageFetchSiz
R/W
Data read page fetch size. This field specifies the number of page table entries to be read by a single read
request packet. 2^(DRPageFetchSize+3) bytes are fetched by single read request. This field defaults to
001b and is unaffected by a bus reset.
1921
DTPageFetchSiz
R/W
Data transmit page fetch size. This field specifies the number of page table entries to be read by single
read request packet. 2^(DTPageFetchSize+3) bytes are fetched by single read request. It defaults to 001b
and is unaffected by a bus reset.
22
Dackpnd
R/W
Data acknowledge pending. When Dackpnd is set to 0, ack_complete acknowledge requests are written
to the BDFIFO rather than ack_pending.
23
Drespcmp
R/W
DRF response complete. When Dackpnd is 0 and Drespcmp is 1, the ack_complete is automatically sent
by AutoResponse.
24
DTHdIs
R/W
DTF header insert mode. When DTHdIs is set to 1, DTx Header0 – 3 at E8h-F4h are inserted as the header
of the data transmitted from the DTF. The chip expects the host to load the DTF with data that contains no
header. When DTHdIs is set to 0, the chip expects the DTF to contain complete formatted 1394 packets.
25
Dpause
R/W
DRF pause. When Dpause is set to 1, the transfer of the packet in the DRF is paused after DRF Header 0 -
3 at D0hDCh and DRF trailer register at E0h are updated. When Dpause is set to 0, the transfer of the
packet in the DRF is continued after DRF Header 0 – 3 at D0hDCh and DRF trailer register at E0h are
updated. This bit defaults to 1.
26
DRStPS
R/W
DRF sets Dpause automatically. When DRStPS is set to 1, the packetizer does not send the next read
request until the receiving data is read from the bulky data interface.
27
DRHStr
R/W
DRF header strip mode. When DRHStr is set to 1, the header is stripped from the packet and only data
payload is delivered to the host. The stripped header is copied to DRF Header 0 – 3 at D0hDCh and DRF
trailer register at E0h.
28
DRDSel
R/W
DRF receiving data destination select. When DRDSel is set to 1, the received packets are transferred to
the host through the bulky DMA I/F. When DRDSel is set to 0, the host has read access to the DRF by
reading received data from DRF data at ACh.
29
DTDSel
R/W
DTF transmitting data source select. When DTDSel is set to 1, the host has write access to the DTF
through the DMA bulky IF. When DTDSel is set to 0, the host has write access to DTF by writing transmitted
data on DTF first and continue register at A4h and DTF update register at A8h.
30
DRFClr
S/C
DRF clear control bit. When DRFClr is set to 1, data in the DRF is cleared. NOTE: (DPP mode) Signal
BDOAvail (9Ch) is not negated after the DRF is cleared. BDORst (94h) must be set after DRFClr.
31
DTFClr
S/C
DTF clear control bit. When DTFClr is set to 1, data in the DTF is cleared.
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