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| 型號： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 94/146頁 |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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325
3.4.31 Bulky Interface Control Register at 94h
This register defaults to 1680 0121 and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
02
Reserved
N/A
Reserved
35
MTRBufSiz
R/W
Specifies DRF status block buffer. MTRBufSiz is the size of the DRF status block buffer in quadlets. These
bits default to 101b and are unaffected by a bus reset (see Note 1).
000b: 0 quadlets, 001b: 2 quadlets, 010b: 4 quadlets, 011b: 6 quadlets,
100b: 8 quadlets, 101b: 10 quadlets, 110b: 12 quadlets, 111b: 14 quadlets
68
MTTBufSiz
R/W
Specifies DTF status block buffer. MTTBufSiz is the size of the DTF status block buffer in quadlets. These
bits default to 101b and is unaffected by a bus reset (see Note 1).
000b: 0 quadlets, 001b: 2 quadlets, 010b: 4 quadlets, 011b: 6 quadlets,
100b: 8 quadlets, 101b: 10 quadlets, 110b: 12 quadlets, 111b: 14 quadlets
9
BDAckCtl
R/W
Active high control for BDACK terminal. When BDAcKCtl is set to 1, BDAck is active high. When BDAcKCtl
is set to 0, BDACK is active low.
10
Reserved
N/A
Reserved
11
ATAckCtl
R/W
Active high control for ATACK terminal. When ATAckCtl is set to 1, ATACK is active high. When AckCtl is
set to 0, ATACK is active low.
12
BIBsyCtl
R/W
Active high control for BDIBUSY terminal. When BIBsyCtl is set to 1, BDIBUSY is active high. When
BIBsyCtl is set to 0, BDIBUSY is active low.
13
BOAvCtl
R/W
Active high control for BDOAVAIL terminal. When BOAvCtl is set to 1, BDOAVAIL is active high. When
BOAvCtl is set to 0, BDOAVAIL is active low.
14
BOEnCtl
R/W
Active high control for BDOEN terminal. When BOEnCtl is set to 1, BDOEN is active high. When BOEnCtl
is set to 0, BDOEN is active low.
15
BIEnCtl
R/W
Active high control for BDIEN terminal. When BIEnCtl is set to 1, BDIEN is active high. When BIEnCtl is set
to 0, BDIEN is active low.
16
BLECtl
R/W
BDIO data little-endian control. When BLECtl is set to 1, the DMA port is in little endian mode.
17
AutoPad
R/W
Automatic padding. When AutoPad is set to 1, data that is not quadlet aligned is automatically padded with
zeros. When AutoPad is set to 0, data that is not quadlet aligned is aligned by the DMA bulky interface.
1821
BDIDelay
R/W
BDIDelay. These bits must be set to 0 when the register is written
2223
BDOMode
R/W
BDOMode. See Section 12. These bits default to 01b and are unaffected by a bus reset.
24
Burst
R/W
Burst mode. When this bit is set to 1, the bulky DMA I/F operates in burst mode.
2527
BDIMode
R/W
BDIMODE. See Section 12. These bits default to 010b and are unaffected by a bus reset.
28
RcvPad
R/W
Received data padding bits to the BDIF. Data must be written through to the BDIF in quadlet multiples. If a
packet does not end on a quadlet boundary, zeros are padded to the last quadlet automatically. When
RcvPad is set to 1, 1394 is allowed to pad bits to the BDIF. The BDIF does not strip the zeros inserted into
received packets prior to transferring them to the BDIF. When RcvPad is set to 0, 1394 is not allowed to pad
bits to the BDIF.
29
BDORst
S/C
BDO logic reset. When BDORst is set to 1, BDO logic is reset. A BDO reset is recommended when 94h is
modified. This bit defaults to 0 and is set to 0 on a bus reset.
30
BDIRst
S/C
BDI logic reset. When BDIRst is set to 1, BDI logic is reset. A BDI reset is recommended when 94h is
modified. This bit defaults to 0 and is set to 0 on a bus reset
31
BDOTris
R/W
BDO 3-state. When BDOTris is set to 1, the BDO data bus, BDIO[15:8], is forced to a high-impedance state
(this does not effect BDREQ). This bit defaults to 1 and is unaffected on a bus reset.
NOTE 1: RAM size (quadlets) is partitioned according to the following equation.
AR_CSR_Siz(8Ch)+DTFPTBufSiz(98h)+DRFPTBufSiz(98h)+MTTBufSiz(94h)+MTRBufSiz(94h)+LOGSize = 126 quadlets
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