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參數(shù)資料
| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 140/146頁(yè) |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
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81
8 BD FIFOs (Total 1182 Quadlets)
The bulky data FIFOs consist of the DTF (data transmit FIFO) and the DRF (data receive FIFO). These FIFOs are
primarily used for large data transfers through the bulky interface, but can be accessed by the host.
8.1
Setting the BD FIFO Size
DTF:
Data transmit FIFO
adjustable
DRF:
Data receive/fetch FIFO
adjustable
8.1.1
DTF
If the auto header insertion mode (DTHdIs = 1 at 90h, bit 24) is selected, the packet payload is written into the DMA
data transmit FIFO (DTF). If this mode is not selected, transmission data including header is written to the DTF.
Considering this, set necessary packet quadlet size for DTF_Size on DTF/DRF size (98h).
After DMA finishes writing one packet of data, it starts a packet transmission request on 1394 bus. For efficiency, it
is recommended that DTF_Size be set to more than double the data size of one request packet. This enables
multiplex packet transmission time and transmission data writing time.
8.1.2
DRF
The complete packet, including the header and trailer of the response packet is written in the data response FIFO
(DRF). This is the same when the response header strip mode is used. Thus, DRF_Size (quadlet) in DTF/DRF size
(98h) needs to be larger than the response header and trailer.
8.2
DTF/DRF Packet Format
The data formats for the transmission and reception of data through the DMA bulky interface are shown in the
following sections. The transmit formats describe the expected organization of data presented to the TSB43AA82
at the DMA bulky interface. The receive formats describe the expected organization of data that the TSB43AA82
presents to the DMA bulky interface.
8.2.1
DRF Packet Format
The DRF packet format shown in Figure 81 describes the data format of the packet received at the DMA bulky
interface. The first quadlet contains the status of the received packet. The first 16 bits of the second quadlet contain
the destination bus and node number, the remaining 16-bits contain packet-control information. The first 16 bits of
the second quadlet contain the bus and node number of the destination node, and the last 16 bits contain packet
control information. The first 16 bits of the third quadlet contain the bus and node number of the source node. The
first 16 bits of the fifth quadlet contain the length of the data and the last 16-bits contain the extended tCodes. All
remaining quadlets contain data that is used only for write requests and read responses. For block read requests and
block write responses, the data field is omitted. Table 8-1 shows a description of each field.
0
1
2
3
4
5
6
7
8
9
10 11
12 13
14 15
16 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31
status
Reserved
spd
Reserved
ack
destination ID
tLabel
rt
tCode
prior
source ID
rCode
Reserved
data_length
extended_tCode
block data
Figure 81. DRF Block-Receive Packet Format
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82PGEG4 | 功能描述:1394 接口集成電路 2Port Hi Per Int Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AB21 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:INTERGRATED 1394A-2000 OHCI PHY LINK-LAYER CONTROLLER |
| TSB43AB21A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
| TSB43AB21A-EP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Military Enhanced Plastic Integrated 1394a-2000 OCHI pHY/Link-Layer Controller |
| TSB43AB21AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Integrated 1394a-2000 OHCI PHY/Link-Layer Controller |
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