參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 9/67頁
文件大小： 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320C209 Pin Functions (Continued)
PIN
I/O/Z
DESCRIPTION
NAME
NO.
TEST SIGNALS
TCK
8
I
JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on TAP
(test access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register,
or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TDI
5
I
JTAG test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of
TCK.
TDO
71
O/Z
JTAG test data output. The contents of the selected register (instruction or data) are shifted out of TDO
on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in
progress. TDO goes into the high-impedance state when OFF is active low.
TMS
32
I
JTAG test mode select. TMS is clocked into the TAP controller on the rising edge of TCK.
TRST
80
I
JTAG test reset. TRST, when active high, gives the JTAG scan system control of the operations of the
device. If TRST is not connected or driven low, the device operates in its functional mode, and the JTAG
signals are ignored.
EMU0
EMU1
2
3
I/O/Z
Emulator pin 0. When TRST is driven low, this pin must be high for activation of the OFF condition. When
TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined an
input/output via JTAG scan.
Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as
an interrupt to or from the emulator system and is defined as input/output via JTAG scan. When TRST
is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the
high-impedance state
SUPPLY PINS
VDD
1
15
50
51
76
PWR
Power.
VSS
12
21
22
29
41
47
56
61
73
PWR
Ground.
I = input, O = output, Z =high impedance
A
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