參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 11/67頁
文件大小： 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 3. Legend for C2xx Block Diagram
SYMBOL
NAME
DESCRIPTION
A
A Input
A input of the two operand CALU. A feeds ACC back to the CALU operations.
AOB
CALU Operation
Identifies the operation of A to B in the CALU. The O can be an arithmetic or logical operation as defined by
the operator selection for the current instruction.
ACC
Accumulator
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities.
ARAU
Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs.
AUX
REGS
Auxiliary Register
0–7
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the ARP, auxiliary register pointer. AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR(ARP).
B
B Input
B input of the two operand CALU. B feeds the 32-bit input (from ISCALE or PSCALE) to the CALU operations.
BR
Bus Register
Signal
BR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available for the bus transaction. BR can be used to extend the data memory
address space by up to 32K words.
C
Carry
Register carry output from CALU. C is feed back into the CALU for extended arithmetic operation. The C bit
resides in ST1, status register 1 and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
CALU
Central Arithmetic
Logic Unit
32-bit wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC and
provides status results to PCTRL.
CNF
On-Chip RAM
Configuration
Control Bit
If set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are
mapped to program space.
DRAB
Data Read
Address Bus
16-bit bus that provides the address for data read operations. DRAB is driven by the TMS320C2xx core.
DRDB
Data-Read Bus
16-bit bus for data-space read data. DRDB is driven by memories or the logic interface.
DWAB
Data-Write Bus
16-bit bus that provides the address for data-write operations. DWAB is driven by the TMS320C2xx core.
DWEB
Data-Write Bus
16-bit bus for data-space write data. DWEB is driven by the TMS320C2xx core.
GREG
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space.
IMR
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
IFR
Interrupt Flag
Register
The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
interrupts.
INTM
Interrupt Mode Bit
When set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INT#
Interrupt Traps
A total of 32 interrupts via hardware and/or software are available.
ISCALE
Input Data-Scaling
Shifter
16 to 32-bit barrel left shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left relative to the 32-bit
output within the fetch cycle therefore not cycle overhead required for input scaling operations.
MPY
Multiplier
16
×
16-bit Multiplier to a 32-bit product. MPY executes multiplication in a single cycle. Operates either signed
or unsigned 2s complement arithmetic multiply.
MSTACK
Micro Stack
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MUX
Multiplexer
Multiplexes buses to a common input.
NPAR
Next Program
Address
NPAR holds the program address to be driven out PAB on the next cycle.
A
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