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參數(shù)資料
| 型號： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關斷，先進的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關斷，先進的外圍，多種鎖相環(huán)可選） |
| 文件頁數(shù)： | 31/67頁 |
| 文件大小： | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiprocessing (’C203 only)
The flexibility of the ’C2xx allows configurations to satisfy a wide range of system requirements; the device can
be used in a variety of system configurations, including but not limited to the following:
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global memory space
A peripheral processor interfaced via processor-controlled signals to another device
For multiprocessing applications, the ’C2xx has the capability of allocating global memory space and
communicating with that space via the BR and ready control signals. Global memory is data memory shared
by more than one device. Global memory access must be arbitrated. The 8-bit memory-mapped global memory
allocation register (GREG) specifies part of the ’C2xx’s data memory as global external memory. The contents
of the register determine the size of the global memory space. If the current instruction addresses an operand
within that space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by
the READY line.
The ’C203 supports direct memory access (DMA) to its external program, data, and I/O spaces using the HOLD
and HOLDA signals. Another device can take complete control of the ’C2xx’s external memory interface by
asserting HOLD low. This causes the ’C2xx to to place its address, data, and control lines in the high-impedance
state and assert HOLDA.
instruction set
The ’C2xx microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upward compatible with the ’C2xx.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies depending upon whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The ’C2xx instruction set provides four basic memory-addressing modes: direct, indirect, immediate and
register.
In direct addressing, the instruction word contains the lower seven bits of the data-memory address. This field
is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory
address. Thus, in the direct-addressing mode, data memory is effectively paged with a total of 512 pages, each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
addressing modes
(continued)
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding
or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, following which the current auxiliary register and ARP can
be modified.
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