參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 54/67頁
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 – JUNE 1995
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory and parallel I/O interface write timing (continued)
A15–A0, PS, DS, IS, RW, and BR timings are all included in the timings referenced to A15–A0 except when
in transition between read and write operations where PS, DS, and IS pulse high [see t
w(MSH)
].
switching characteristics over recommended operating conditions @ 5 V [H = 0.5t
c(CO)
]
PARAMETER
’320C2XX-40
MIN
’320C2XX-57
MIN
’320C2XX-80
MIN
UNIT
MAX
MAX
MAX
tsu(A)W
th(A)W
tsu(A)CO
th(A)COw
tw(NSN)
tw(WL)
tw(WH)
td(CO-W)
td(WRD)
tsu(D)W
th(D)W
tsu(DCOL)W
th(DCOL)W
ten(D)W
Values derived from characterization data and not tested.
Setup time, address valid before WE low
H – 7
H – 7
H – 6
ns
Hold time, address valid after WE high
H – 10
H – 10
H – 8
ns
Setup time, address valid before CLKOUT1 low
H – 9
H – 9
H – 8
ns
Hold time, address valid after CLKOUT1 low
Pulse duration, IS, DS, PS inactive high
H – 3
H – 3
H – 2
ns
H – 9
H – 9
H – 8
ns
Pulse duration, WE low (no wait states)
2H – 2
2H + 2
2H – 2
2H + 2
2H – 2
2H + 2
ns
Pulse duration, WE high
2H – 2
2H – 2
2H – 2
ns
Delay time, CLKOUT1 low to WE low/high
0
6
0
6
0
6
ns
Delay time, WE high to RD low
3H – 10
3H – 8
3H – 8
ns
Setup time, write data valid before WE high
2H – 15
2H
H + 7
2H
H + 11
2H – 15
2H
H + 7
2H
H + 11
2H – 14
2H
H + 7
2H
H + 11
ns
Hold time, write data valid after WE high
H – 4
H – 4
H – 3
ns
Setup time, write data valid before CLKOUT1 low
2H – 20
2H – 20
2H – 20
ns
Hold time, write data valid after CLKOUT1 low
Enable time, WE to data bus driven
H – 4
H – 4
H – 5
ns
– 4
– 4
– 3
ns
switching characteristics over recommended operating conditions @ 3 V [H = 0.5t
c(CO)
]
PARAMETER
’320VC2XX-40
’320VC2XX-57
UNIT
MIN
H – 5
MAX
tsu(A)W
th(A)W
tsu(A)CO
th(A)COw
tw(NSN)
tw(WL)
tw(WH)
td(CO-W)
td(WRD)
tsu(D)W
th(D)W
tsu(DCOL)W
th(DCOL)W
ten(D)W
Values derived from characterization data and not tested.
Setup time, address valid before WE low
ns
Hold time, address valid after WE high
H – 10
ns
Setup time, address valid before CLKOUT1 low
H – 9
ns
Hold time, address valid after CLKOUT1 low
Pulse duration, IS, DS, PS inactive high
H – 3
ns
H – 9
ns
Pulse duration, WE low (no wait states)
2H – 2
2H + 2
ns
Pulse duration, WE high
2H – 2
ns
Delay time, CLKOUT1 low to WE low/high
0
6
ns
Delay time, WE high to RD low
3H – 8
ns
Setup time, write data valid before WE high
2H – 15
2H
H + 7
2H
ns
Hold time, write data valid after WE high
H – 4
ns
Setup time, write data valid before CLKOUT1 low
2H – 20
ns
Hold time, write data valid after CLKOUT1 low
Enable time, WE to data bus driven
H – 4
H + 11
ns
– 4
ns
A
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