參數(shù)資料
型號(hào)： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 4/67頁
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
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DIV2
5
DIV1–DIV2 should not be changed unless the RS signal is active.
I = input, O = output, Z =high impedance
PIN
MEMORY CONTROL SIGNALS (CONTINUED)
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DESCRIPTION
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high-impedance state when OFF is active low.
MULTI-PROCESSING SIGNALS
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BR
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98
O/Z
multiprocessing configurations or as a general-purpose output pin. XF goes into the high-impedance state
when OFF is active low.
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O/Z
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high-impedance state when OFF is active low.
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active low.
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Bus request signal. BR is asserted when a global data memory access is initiated. BR goes into the
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A
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If BIO is not used it should be pulled high.
O/Z
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that the address, data, and memory control lines are in the high-impedance state so that they are available to
the external circuitry for access of local memory. HOLDA goes into the high-impedance state when OFF is
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External flag output (latched software-programmable signal). XF is used for signalling other processors in
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IO2
IO3
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IO0
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9
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96
97
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I/O/Z
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Software controlled Input/output pins via the asynchronous serial port register (ASPCR). At reset these pins
are configured as inputs. These can be used as general purpose input/output pins or as handshake control
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RS
100
I
When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS affects
various registers and status bits.
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the on-chip bootloader transfers data from external global data space to external RAM program space.
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BOOT
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2
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Microprocessor mode select pin. When BOOT is high the device accesses off-chip memory. If BOOT is low,
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NMI
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17
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HOLD has priority over INT1 at reset.
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Nonmaskable interrupt. NMI is an external interrupt that cannot be masked via the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled
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INT3
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bit (INTM). Can be polled and reset via the interrupt flag register (IFR). If these signals are not used, they should
be pulled high. INT1/HOLD can select a hold mode where the address, data, and control lines are 3-stated.
I
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1
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X1
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13
CLKOUT1
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O
15
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O/Z
latch phase.
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Master clock ouput signal. The CLKOUT1 high pulse signifies the logic phase while the low pulse signifies the
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operation or can bypass the PLL and operate in a divide-by-two mode. As X2, the pin operates as the oscillator
相關(guān)PDF資料
PDF描述
TN-83 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-101 CONNECTOR ACCESSORY
TN-102 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-103 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-104 CONNECTOR ACCESSORY
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