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參數(shù)資料
| 型號： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進的外圍，多種鎖相環(huán)可選） |
| 文件頁數(shù)： | 29/67頁 |
| 文件大?。?/td> | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320C203 (continued)
Table 14. ’C203 Wait-State Generator Control Register (WSGR)
BITS
NAME
DESCRIPTION
2–0
PSLWS
External program-space wait states (lower). PSLWS determines that between 0,. . .,7 wait states are applied to
all reads and writes to off-chip lower program space address (0h-7FFFh). The memory cycle can be further
extended using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset, (RS).
5–3
PSUWS
External program-space wait states (upper). PSUWS determines that between 0,. . .,7 wait states are applied
to all reads and writes to off-chip upper program space address (8000h-0FFFFh). The memory cycle can be fur-
ther extended using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset, (RS).
8–6
DSWS
External data space wait states. DSWS determines that between 0,. . .,7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset, (RS).
11–9
ISWS
External input /output-space wait state. DSWS determines that between 0,. . .,7 wait states are applied to all
reads to all reads and writes to off-chip I/O space. The memory cycle can be further extended using the READY
signal. The READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active)
by reset, (RS).
15–12
X
Don’t care.
timer
The ’C2xx features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one
thirty-second the machine rate of the device itself, depending upon the programmable timer’s divide-down ratio.
This timer can be stopped, restarted, reset, or disabled by specific status bits.
The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every
CLKOUT1 cycle. A timer interrupt (TINT) and a pulse equal to the duration of a CLKOUT1 cycle on the external
TOUT pin are generated each time the counter decrements to zero. The timer thus provides a convenient means
of performing periodic I/O or other functions.
TMS320C209 input clock options
The TMS320C209 includes two clock options. The first option (
÷
2) operates the CPU at half the input clock rate.
The second option (
×
2) doubles the input clock and phase locks the output clock with the input clock. The
÷
2
mode is enabled by tying the CLKMOD pin low. The
×
2 mode is enabled by tying the CLKMOD pin high.
The clock doubler option of the ’C209 uses an internal phase lock loop (PLL). The PLL requires approximately
1000 cycles to lock. The rising edge of RS (or falling edge of RS) must be delayed until at least three cycles
after the PLL has stabilized. Likewise, the modes cannot be dynamically switched because the internal clock
generator can generate minimal clock pulse with violations. The RS or RS signals should be in their active state
if the CLKMOD pin is changed.
TMS320C203 input clock options
The TMS320C203 provides multiple clock modes of:
÷
2,
×
1,
×
2,
×
4. The clock mode configuration cannot be
dynamically changed without executing another reset. The operation of the PLL circuit is affected by the
operating voltage of the device. If the device is operating at 5 V then the PLL5V signal should be tied high. For
3 V operation, PLL5V should be tied low.
A
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