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參數(shù)資料
| 型號： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選） |
| 文件頁數(shù)： | 12/67頁 |
| 文件大?。?/td> | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 3. Legend for C2xx Block Diagram (Continued)
SYMBOL
NAME
DESCRIPTION
OSCALE
Output
Data-Scaling
Shifter
32 to 16-bit barrel left shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high or low half of the shifted 32-bit data to DWEB.
PAB
Program Address
Bus
16-bit bus that provides the address for program space reads and writes. PAB is driven by the TMS320C2xx
core.
PAR
Program Address
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current machine cycle.
PC
Program Counter
Increments the value from NPAR to provide sequential addresses for instruction fetching and sequential data
transfer operations.
PCTRL
Program
Controller
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
PM
Product Register
Shift Mode Bit
These two bits identify which of the four shift modes (0, 1, 4, -6) will be used by PSCALE. PM resides in ST1.
PRDB
Program Read
Data Bus
16-bit bus for program space read data. PRDB is driven by the memories or the logic interface.
PREG
Product Register
32-bit register holds results of 16
×
16 multiply.
0, 1 or 4-bit left shift or 6-bit right shift of multiplier product. The left shift options are used to manage the
additional sign bits resulting from the 2s complement multiply. The right shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and either the CALU or the DWEB and requires no cycle overhead.
PSCALE
Product-Scaling
Shifter
TREG
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds dynamic shift count for
LACT, ADDT, and SUBT instructions. TREG holds dynamic bit position for BITT instruction.
SSPCR
Synchronous
Serial Port Control
Register
Control register for selecting the mode of operation of the serial port.
SDTR
Synchronous
Serial Port
Transmit and
Receive Register
Data transmit and receive register.
TCR
Timer-Control
Register
TCR contains the control bits that define the divide-down ratio, start/stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer-divide-down ratio to
0 and starts the timer.
PRD
Timer-Period
Register
PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to 0xFFFF.
TIM
Timer-Counter
Register
TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF.
UART
Universal
Asynchronous
Receive Transmit
Asynchronous serial port.
ASPCR
Asynchronous
Serial Port Control
Register
ASPCR controls the asynchronous serial port operation.
IOSR
I/O Status
Register
IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and status of UART.
BRD
Baud Rate Divisor
Used to set the baud rate of the UART.
A
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