參數(shù)資料
型號(hào)： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁(yè)數(shù)： 26/67頁(yè)
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
external interface (continued)
Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When
transactions are made with slower devices, the ’C2xx processor waits until the other device completes its
function and signals the processor via the READY line. Once a ready indication is provided back to the ’C2xx
from the external device, execution continues.
On the ’C209 device, the READY line is required (active high)
to complete reads or writes to internal I/O-mapped registers.
The bus request (BR) signal is used in conjunction with the other ’C2xx interface signals to arbitrate external
global memory accesses. Global memory is external data memory space in which the BR signal is asserted at
the beginning of the access. When an external global memory device receives the bus request, it responds by
asserting the READY signal after the global memory access is arbitrated and the global access is completed.
The TMS320C2xx supports zero-wait state reads on the external interface. However, to avoid bus conflicts,
writes take two cycles. This allows the TMS320C2xx to buffer the transition of the data bus from input to output
(or output to input) by a half cycle. In most systems, TMS320C2xx ratio of reads to writes is significantly large
to minimize the overhead of the extra cycle on writes.
Wait states can be generated when accessing slower external resources. The wait states operate on
machine-cycle boundaries and are initiated either by using READY or using the software wait-state generator.
READY can be used to generate any number of wait states.
interrupts and subroutines
The ’C2xx implements four general-purpose interrupts, INT3–INT1, along with reset (RS) and the nonmaskable
interrupt (NMI) which are available for external devices to request the attention of the processor. Internal
interrupts are generated by the serial port (RINT and XINT) (’C203 only), by the timer (TINT), UART, TXRXINT
(’C203 only), and by the software-interrupt (TRAP, INTR and NMI) instructions. Interrupts are prioritized with
RS having the highest priority, followed by NMI, and timer (’C209) or UART (’C203) having the lowest priority.
Additionally, any interrupt except RS and NMI can be individually masked with a dedicated bit in the interrupt
mask register (IMR) and can be cleared, set, or tested using its own dedicated bit in the interrupt flag register
(IFR). The reset and NMI functions are not maskable.
All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in
those locations if desired.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to
instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because
of wait states.
Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack,
providing a mechanism for returning to the previous context. The stack contains eight locations, allowing
interrupts or subroutines to be nested up to eight levels deep.
reset
The TMS320C203 provides an active-low reset (RS) only, while the TMS320C209 provides both an RS and an
RS.
RS and RS, the TMS320C209 resets, are not synchronized. A minimum pulse duration of six cycles assures
that an asynchronous reset signal resets the device. Either RS or RS can reset the device with RS being active
high and RS being active low. The TMS320C2xx fetches its first instruction approximately sixteen cycles after
the rising edge of RS (either ’C203 or ’C209) or falling edge of RS (’C209 only).
A
相關(guān)PDF資料
PDF描述
TN-83 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-101 CONNECTOR ACCESSORY
TN-102 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-103 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-104 CONNECTOR ACCESSORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320VC33PGE120 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC33PGE-120 制造商:Texas Instruments 功能描述:IC DSP PROCESSOR 320VC33 LQFP144 制造商:Texas Instruments 功能描述:IC, DSP PROCESSOR, 320VC33, LQFP144
TMS320VC33PGE-120 制造商:Texas Instruments 功能描述:IC DSP PROCESSOR 320VC33 LQFP144
TMS320VC33PGE120G4 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC33PGE150 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*