參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 15/67頁
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 4. Status Register Field Definitions
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FIELD
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FUNCTION
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to branch on the status of C. C is set to 1 on a reset.
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DP
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Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory
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Carry Bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
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is loaded by the SPM and LST #1 instructions. PM is cleared by RS.
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Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the
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central processing unit
The TMS320C2xx central processing unit (CPU) contains a 16-bit scaling shifter, a 16x16-bit parallel multiplier,
a 32-bit arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the
accumulator and the multiplier. This section describes the CPU components and their functions. The functional
block diagram (page 10) shows the components of the CPU.
input scaling shifter
The TMS320C2xx provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
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