參數(shù)資料
型號(hào)： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁(yè)數(shù)： 24/67頁(yè)
文件大小： 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory (continued)
Table 10. TMS320C203 Memory and I/O Internally Mapped Registers
NAME
ADDRESS
DESCRIPTION
IMR
DS@0004
Interrupt-mask register. IMR individually masks or enables the seven interrupts. Bit 0 shares the external interrupt
pins INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2 ties to the timer interrupt, TINT. Bits 3 and 4, RINT and
XINT, respectively, are for the synchronous serial port, SSP. Bit 5, TXRXINT shares the transmit and receive
interrupts for the asynchronous serial port, ASP. Bit 6 is reserved for monitor mode emulation operations and
should always be set to 0 except in conjunction with emulation monitor operations. Bits 7–15 are not used in the
TMS320C203. IMR is set to 0 at reset.
GREG
DS@0005
Global-memory-allocation register. GREG specifies the size of the global memory space. GREG is set to 0 at
reset.
IFR
DS@0006
Interrupt-flag register. IFR indicates that the TMS320C203 has latched an interrupt from one of the seven
maskable interrupts. Bit 0 shares the external interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2 ties to
the timer interrupt, TINT. Bits 3 and 4, RINT and XINT, respectively, are for the synchronous serial port, SSP. Bit
5, TXRXINT shares the transmit and receive interrupts for the asynchronous serial port, ASP. Bit 6 is reserved
for monitor mode emulation operations and should always be set to 0 except in conjunction with emulation monitor
operations. Writing a 1 to the respective interrupt bit clears an active flag and the respective pending interrupt.
Writing a 1 to an inactive flag has no effect. Bits 7–15 are not used in the TMS320C203. IMR is set to 0 at reset.
CLK
IS@FFE8
CLKOUT1 on or off. At reset, this bit is configured as a zero for the CLKOUT1 pin to be active. If CLKOUT1 is
a 1, CLKOUT1 pin is turned off.
IC
IS@FFEC
Interrupt control register. IC is used to determine which interrupt is active since INT1 and HOLD share an interrupt
vector as do INT1 and INT3. A portion of this register is for mask/unmask (similar to IMR) and another portion
is for pending interrupts (similar to IFR). At reset, all bits are zeroed, enabling HOLD mode. The MODE bit is used
by the hold generating circuit to determine if a HOLD or INT1 is active.
SDTR
IS@FFF0
Synchronous serial port (SSP) transmit and receive register.
SSPCR
IS@FFF1
Synchronous serial port control register.
ADTR
IS@FFF4
Asynchronous serial port (ASP) transmit and receive register.
ASPCR
IS@FFF5
Asynchronous serial port control register. ASPCR controls the asynchronous serial port operation.
IOSR
IS@FFF6
I/O status register. IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and status of UART.
BRD
IS@FFF7
Baud rate divisor. Used to set baud rate of UART.
TCR
IS@FFF8
Timer-control register. TCR contains the control bits that define the divide-down ratio, start/stop the timer, and
reload the period. Also contained in TCR is the current count in the prescaler. Reset initializes the
timer-divide-down ratio to 0 and starts the timer.
BRD
IS@FFF9
Timer-period register. PRD contains the 16-bit period that is loaded into the timer counter when the counter
borrows or when the reload bit is activated. Reset initializes the PRD to 0xFFFF.
TIM
IS@FFFA
Timer-counter register. TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF.
WSGR
IS@FFFC
Wait-state-generator register. WSGR contains 12 control bits to enable 0, . . . ,7 wait states to program, data, and
I/O space. Reset initializes the WSGR to 0x0FFFh.
A
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