參數(shù)資料
型號(hào): TMS320VC203
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(50ns指令周期, 空閑狀態(tài)CPU全關(guān)斷,先進(jìn)的外圍,多種PLL可選)
中文描述: 數(shù)字信號(hào)處理器(50ns的指令周期,空閑狀態(tài)CPU的全關(guān)斷,先進(jìn)的外圍,多種鎖相環(huán)可選)
文件頁(yè)數(shù): 51/67頁(yè)
文件大?。?/td> 1452K
代理商: TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 – JUNE 1995
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
CI
C0
D
IN
A[15:0]
CLKIN/X2
CLKOUT1
D[15:0]
INT[3:1] or INTx
MS
R
RD
RS
W
Memory strobe pins IS, DS or PS
READY
Read cycle or RD
RESET pins RS or RS
Write cycle or WE
Lowercase subscripts and their meanings are:
a
access time
c
cycle time (period)
d
delay time
f
full time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
The following letters and symbols and their meanings are:
H
High
L
Low
V
Valid
Z
High impedance
X
Unknown, changing, or don’t care level
general notes on timing parameters
All output signals from the TMS320C2xx devices (including CLKOUT1) are derived from an internal clock such
that all output transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
A
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