參數(shù)資料
型號: ST72124J2B7
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
中文描述: 8位單電壓閃存,ADC和16位定時器,SPI和脊髓損傷界面微控制器
文件頁數(shù): 96/125頁
文件大小: 776K
代理商: ST72124J2B7
ST72334J/N, ST72314J/N, ST72124J
96/125
8-BIT A/D CONVERTER (ADC)
(Cont’d)
6.7.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
AIN
) is greater than or equal
to V
DDA
(high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
AIN
) is lower than or equal to
V
SSA
(low-level voltage reference) then the con-
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
Electrical CharacteristicsSection.
R
AIN
is the maximum recommended impedance
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
6.7.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 57:
I
Sample capacitor loading
[duration: t
LOAD
]
During this phase, the V
AIN
input voltage to be
measured is loaded into the C
SAMPLE
sample
capacitor.
I
A/D conversion
[duration: t
CONV
]
During this phase, the A/D conversion is
computed (8successive approximations cycles)
and
the
C
SAMPLE
disconnected from the analog input pin to get
the optimum A/D conversion accuracy.
While theADC is on, these two phasesare contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
6.7.3.4 Software Procedure
Refer tothe control/status register(CSR) and data
register (DR) inSection 6.7.6 for the bit definitions
and to Figure 57 for the timings.
sample
capacitor
is
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
ADC
=2/f
CPU
).
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the I/O
ports chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog
channel to convert.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter
and tostart the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 57. ADC Conversion Timings
6.7.4 Low Power Modes
Note:
The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions..
6.7.5 Interrupts
None
Mode
WAIT
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, theA/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
HALT
ADCCSR WRITE
OPERATION
ADON
COCO BIT SET
t
LOAD
t
CONV
HOLD
CONTROL
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