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參數(shù)資料
| 型號： | ST72124J2B7 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| 中文描述： | 8位單電壓閃存，ADC和16位定時器，SPI和脊髓損傷界面微控制器 |
| 文件頁數(shù)： | 121/125頁 |
| 文件大小： | 776K |
| 代理商： | ST72124J2B7 |
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ST72334J/N, ST72314J/N, ST72124J
121/125
9.2 DEVICE CONFIGURATION AND ORDERING
INFORMATION
Each deviceis available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM).
FLASH devices are shipped to customers with a
default content (FFh), while ROM factory coded
parts contain the code supplied by the customer.
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes
while the ROM devices are factory-configured.
9.2.1 Option Bytes
The two Option Bytes allow the hardware configu-
ration of the microcontroller to be selected.
The Option Bytes have no address in the memory
map and can be accessed only in programming
mode
(for
example
using
4programming tool). The default contents of the
FLASH is fixed to FFh. This means that all the op-
tions have “1” as their default value.
In masked ROM devices, the Option Bytes are
fixed in hardware by the ROM code.
a
standard
ST7
USER OPTION BYTE 1
Bit 7:2 = Reserved, must always be 1.
Bit 1 =
56/42
Package configuration
This option bit allows to configure the device ac-
cording to the package.
0: 42 and 44 pin.
1: 56 and 64 pin.
Bit 0 =
FMP
Full memory protection.
This option bit enables ordisables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected
USER OPTION BYTE 2
Bit 7 =
CFC
Clock filter control on/off
This option bit enables or disables the clock filter
(CF) features.
0: Clock filter enabled
1: Clock filter disabled
Bit 6:4 =
OSC[2:0]
Oscillator selection
These three option bits can be used to select the
main oscillator as shown in Table 24.
Table 24. Main Oscillator Configuration
Bit 3:2 =
LVD[1:0]
Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in Table 25.
Table 25. LVD Threshold Configuration
Bit 1 =
WDG HALT
Watchdog and halt mode
This option bit determines ifa RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 =
WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
7
0
1
1
1
1
1
1
56/42
FMP
7
0
CFC OSC2 OSC1 OSC0 LVD1 LVD0
WDG
HALT
WDG
SW
Selected Oscillator
External Clock (Stand-by)
Internal RC
OSC2
1
1
1
1
0
0
0
0
OSC1 OSC0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
External RC
Low Speed Resonator
Medium-low Speed Resonator
Medium-high Speed Resonator
High Speed Resonator
Configuration
LVD1 LVD0
LVD Off
1
1
Highest Voltage Threshold (V
DD
~5V)
Medium Voltage Threshold (f
OSC
≤
16MHz)
Lowest Voltage Threshold (f
OSC
≤
8MHz)
1
0
0
1
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72124J2B7/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T1/XXX | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
| ST72124J2T3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES |
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